Inventor

EMER JOEL S

US37 patents

⚠️ This page may combine multiple inventors who share the name “EMER JOEL S”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

EMER JOEL S

INTEL CORP

Incremental checkpointing in a multi-threaded architecture

Detecting errors in directory entries

Hardware recovery in a multi-threaded architecture

Periodic checkpointing in a redundantly multi-threaded architecture

Executing distributed memory operations using processing elements connected by distributed channels

Method and apparatus for reducing false error detection in a redundant multi-threaded system

Implementing check instructions in each thread within a redundant multithreading environments

Reducing the uncorrectable error rate in a lockstepped dual-modular redundancy system

Managing external memory updates for fault detection in redundant multithreading systems using speculative memory support

Method and apparatus for reducing false error detection in a microprocessor

Reducing false error detection in a microprocessor by tracking instructions neutral to errors

Executing distributed memory operations using processing elements connected by distributed channels

STEELY JR SIMON C

Efficient support of sparse data structure access

Signature based hit-predicting cache

Short circuit of probes in a chain

Domain state

Method and apparatus for optimizing the usage of cache memories

Retrieval of previously accessed data in a multi-core processor

High bandwidth full-block write commands

DIGITAL EQUIPMENT CORP

Method and apparatus for predicting memory dependence using store sets

Apparatus and method for speculatively executing instructions in a computer system

Multiprobe instruction cache with instruction-based probe hint generation and training whereby the cache bank or way to be accessed next is predicted

Integrated circuit chip having primary and secondary random access memories for a hierarchical cache

Mechanism for enforcing the correct order of instruction execution

Method and apparatus for propagating exception conditions of a computer system

HEWLETT PACKARD DEVELOPMENT CO

Temporary halting of thread execution until monitoring of armed events to memory location identified in working registers

Software controlled pre-execution in a multithreaded processor

Flexible demand-based resource allocation for multiple requestors in a simultaneous multi-threaded CPU

Mechanism for executing computer instructions in parallel

Branch prediction combining static and dynamic prediction techniques

COMPAQ COMPUTER CORP

System for passing an index value with each prediction in forward direction to enable truth predictor to associate truth value with particular branch instruction

Thread properties attribute vector based thread selection in multithreading processor

Pipelined multi-thread processor selecting thread instruction in inter-stage buffer based on count information

Method and apparatus for employing a cycle bit parallel executing instructions

COMPAQ INFORMATION TECHNOLOGIE

Method and apparatus to quiesce a portion of a simultaneous multithreaded central processing unit

NVIDIA CORP

Scalable multi-die deep learning system

JALEEL AAMER

Method and apparatus for achieving non-inclusive cache performance with inclusive caches