Inventor
SALMON JOSEPH H
US26 patents
⚠️ This page may combine multiple inventors who share the name “SALMON JOSEPH H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
21 patentsUS6421801B1Jul 16, 2002
Testing IO timing in a delay locked system using separate transmit and receive loops
INTEL CORP98 citations97
US7194559B2Mar 20, 2007
Slave I/O driver calibration using error-nulling master reference
INTEL CORP38 citations92
US6941484B2Sep 6, 2005
Synthesis of a synchronization clock
INTEL CORP29 citations92
US6885959B2Apr 26, 2005
Circuit and method for calibrating DRAM pullup Ron to pulldown Ron
INTEL CORP35 citations92
US6195759B1Feb 27, 2001
Method and apparatus for operating a synchronous strobe bus
INTEL CORP19 citations92
US5077738ADec 31, 1991
Test mode enable scheme for memory
INTEL CORP49 citations92
US5057715AOct 15, 1991
CMOS output circuit using a low threshold device
INTEL CORP42 citations92
US5216289AJun 1, 1993
Asynchronous reset scheme for ultra-low noise port tri-state output driver circuit
INTEL CORP36 citations89
US5159672AOct 27, 1992
Burst EPROM architecture
INTEL CORP24 citations89
US6236250B1May 22, 2001
Circuit for independent power-up sequencing of a multi-voltage chip
INTEL CORP15 citations84
US6381722B1Apr 30, 2002
Method and apparatus for testing high speed input paths
INTEL CORP16 citations83
US5490109AFeb 6, 1996
Method and apparatus for preventing over-erasure of flash EEPROM memory devices
INTEL CORP15 citations74
US5170073ADec 8, 1992
Ultra-low noise port output driver circuit
INTEL CORP18 citations73
US5574857ANov 12, 1996
Error detection circuit for power up initialization of a memory array
INTEL CORP18 citations70
US6260105B1Jul 10, 2001
Memory controller with a plurality of memory address buses
INTEL CORP6 citations68
US5298807AMar 29, 1994
Buffer circuitry for transferring signals from TTL circuitry to dual range CMOS circuitry
INTEL CORP17 citations67
US5533196AJul 2, 1996
Method and apparatus for testing for a sufficient write voltage level during power up of a SRAM array
INTEL CORP3 citations63
US5379249AJan 3, 1995
UPROM programming protect circuit
INTEL CORP6 citations63
US6973603B2Dec 6, 2005
Method and apparatus for optimizing timing for a multi-drop bus
INTEL CORP3 citations62
US5257221AOct 26, 1993
Apparatus for selecting mumber of wait states in a burst EPROM architecture
INTEL CORP6 citations62
US7117401B2Oct 3, 2006
Method and apparatus for optimizing timing for a multi-drop bus
INTEL CORP0 citations52
BAINS KULJIT S
3 patentsUS8595428B2Nov 26, 2013
Memory controller functionalities to support data swizzling
BAINS KULJIT S16 citations84
US8132074B2Mar 6, 2012
Reliability, availability, and serviceability solutions for memory technology
BAINS KULJIT S4 citations63
US8392796B2Mar 5, 2013
Reliability, availability, and serviceability solution for memory technology
BAINS KULJIT S0 citations52