Inventor
NAKADA TAKEO
JP9 patents
⚠️ This page may combine multiple inventors who share the name “NAKADA TAKEO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
6 patentsUS5222229AJun 22, 1993
Multiprocessor system having synchronization control mechanism
IBM167 citations96
US5265215ANov 23, 1993
Multiprocessor system and interrupt arbiter thereof
IBM51 citations88
US6049852AApr 11, 2000
Preserving cache consistency in a computer system having a plurality of memories with overlapping address ranges
IBM18 citations80
US5913225AJun 15, 1999
Cache flush mechanism for a secondary cache memory
IBM8 citations73
US10237058B2Mar 19, 2019
Identification of artificail object and artifical object used therein
IBM4 citations72
US7315964B2Jan 1, 2008
Digital signal measuring apparatus and traffic observing method
IBM3 citations62
HARADA NOBUYUKI
3 patentsUS8266385B2Sep 11, 2012
Technique and apparatus for identifying cache segments for caching data to be written to main memory
HARADA NOBUYUKI2 citations60
US8683142B2Mar 25, 2014
Technique and apparatus for identifying cache segments for caching data to be written to main memory
HARADA NOBUYUKI1 citations49
US8112589B2Feb 7, 2012
System for caching data from a main memory with a plurality of cache states
HARADA NOBUYUKI0 citations39