Inventor
TRIVEDI ROMESH B
US5 patents
Patents
5 patentsUS10229735B1Mar 12, 2019
Block management for dynamic single-level cell buffers in storage devices
INTEL CORP57 citations96
US6745337B1Jun 1, 2004
Glitch detection circuit for outputting a signal indicative of a glitch on a strobe signal and initializing an edge detection circuit in response to a control signal
INTEL CORP27 citations85
US10650886B2May 12, 2020
Block management for dynamic single-level cell buffers in storage devices
INTEL CORP2 citations71
US6915407B2Jul 5, 2005
Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller
INTEL CORP8 citations69
US6748513B1Jun 8, 2004
Method and apparatus for a low latency source-synchronous address receiver for a host system bus in a memory controller
INTEL CORP10 citations69