Inventor

LEE SI-WOO

US65 patents

⚠️ This page may combine multiple inventors who share the name “LEE SI-WOO”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

LEE SI-WOO

MICRON TECHNOLOGY INC

Methods of forming an elevationally extending conductor laterally between a pair of conductive lines

Underbody contact to horizontal access devices for vertical three-dimensional (3D) memory

Vertical digit line for semiconductor devices

Vertical digit lines for semiconductor devices

Storage node after three-node access device formation for vertical three dimensional (3D) memory

Apparatuses having memory strings compared to one another through a sense amplifier

Apparatuses having memory strings compared to one another through a sense amplifier

Passing access line structure in a memory device

Digit line and body contact for semiconductor devices

Channel conduction in semiconductor devices

Self-aligned etch back for vertical three dimensional (3D) memory

Channel and body region formation for semiconductor devices

Array of vertical transistors and method used in forming an array of vertical transistors

Channel integration in a three-node access device for vertical three dimensional (3D) memory

Single crystal horizontal access device for vertical three-dimensional (3D) memory and method of forming 3D memory

Single crystalline silicon stack formation and bonding to a CMOS wafer

Gate dielectric repair on three-node access device formation for vertical three-dimensional (3D) memory

Epitaxtal single crystalline silicon growth for a horizontal access device

Replacement gate dielectric in three-node access device formation for vertical three dimensional (3D) memory

Integrated assemblies having threshold-voltage-inducing-structures proximate gated-channel-regions, and methods of forming integrated assemblies

Passing access line structure in a memory device

Microelectronic devices including semiconductive pillar structures, and related electronic systems

Digit line formation for horizontally oriented access devices

Apparatuses including threshold voltage compensated sense amplifiers and methods for compensating same

Vertical digit lines for semiconductor devices

Vertical digit line for semiconductor devices

Array of vertical transistors and method used in forming an array of vertical transistors

Epitaxial single crystalline silicon growth for a horizontal access device

Single crystalline silicon stack formation and bonding to a cmos wafer

Microelectronic devices and memory devices

Recessed channel fin integration

Single crystalline silicon stack formation and bonding to a CMOS wafer

Epitaxial silicon within horizontal access devices in vertical three dimensional (3D) memory

DRAM circuitry, and integrated circuitry

Integrated assemblies having threshold-voltage-inducing-structures proximate gated-channel-regions, and methods of forming integrated assemblies

Channel conduction in semiconductor devices

Methods of forming microelectronic devices

Integrated assemblies which include non-conductive-semiconductor-material and conductive-semiconductor-material, and methods of forming integrated assemblies

Multiple, alternating epitaxial silicon for horizontal access devices in vertical three dimensional (3D) memory

Vertical digit lines with alternating epitaxial silicon for horizontal access devices in 3D memory

Conductive line contact regions having multiple multi-direction conductive lines and staircase conductive line contact structures for semiconductor devices

Vertically stacked storage nodes and access devices with horizontal access lines

Bottom electrode contact for a vertical three-dimensional memory

Microelectronic devices including semiconductive pillar structures, and related electronic systems

SAMSUNG ELECTRONICS CO LTD

Multilayer passivation process for forming air gaps within a dielectric between interconnections

Semiconductor memory device having capacitor for peripheral circuit

HYNIX SEMICONDUCTOR INC

Semiconductor device for preventing inflow of high current from an input/output pad and a circuit for preventing inflow of high current thereof

Electrostatic discharge protection circuit and electrostatic discharge protection method of a semiconductor memory device

KOREA ENERGY RESEARCH INST

Top foil for foil thrust bearing and foil thrust bearing including the same

LODESTAR LICENSING GROUP LLC

Channel conduction in semiconductor devices