Inventor

POTEET KENNETH A

US21 patents

⚠️ This page may combine multiple inventors who share the name “POTEET KENNETH A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

POTEET KENNETH A

TEXAS INSTRUMENTS INC

System including a data processor, a synchronous dram, a peripheral device, and a system clock

Apparatus and method for a memory unit with a processor integrated therein

Random access memory arranged for operating synchronously with a microprocessor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

Memory module arranged for data and parity bits

Memory module arranged for data and parity bits

Fuse selectable timing signals for internal signal generators

Detector and integrated circuit device including charge pump circuits for high load conditions

Process of making and a DRAM standby charge pump with oscillator having fuse selectable frequencies

Data processing system arranged for operating synchronously with a high speed memory

Random access memory with latency arranged for operating synchronously with a micro processor and a system including a data processor, a synchronous DRAM, a peripheral device, and a system clock

High-speed memory arranged for operating synchronously with a microprocessor

High speed memory arranged for operating synchronously with a microprocessor

Dual receiver edge-triggered digital signal level detection system

Method and apparatus for implementing ×2 parity DRAM for 16 bit systems from ×4 parity DRAM

ALLIANCE SEMICONDUCTOR CORP

Staggered pipeline access scheme for synchronous random access memory

Reduced area word line driving circuit for random access memory

Burst random access memory employing sequenced banks of local tri-state drivers

Timing control circuit for synchronous static random access memory

Dual-port random access memory having reduced architecture

Random access memory redundancy circuit employing fusible links

Staggered pipeline access scheme for synchronous random access memory