Inventor
WOTTRENG ANDREW H
US16 patents
⚠️ This page may combine multiple inventors who share the name “WOTTRENG ANDREW H”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
IBM
10 patentsUS6088788AJul 11, 2000
Background completion of instruction and associated fetch request in a multithread processor
IBM123 citations95
US6334167B1Dec 25, 2001
System and method for memory self-timed refresh for reduced power consumption
IBM52 citations93
US5333297AJul 26, 1994
Multiprocessor system having multiple classes of instructions for purposes of mutual interruptibility
IBM37 citations92
US6880113B2Apr 12, 2005
Conditional hardware scan dump data capture
IBM24 citations89
US7631131B2Dec 8, 2009
Priority control in resource allocation for low request rate, latency-sensitive units
IBM11 citations83
US4358826ANov 9, 1982
Apparatus for enabling byte or word addressing of storage organized on a word basis
IBM8 citations70
US7721023B2May 18, 2010
I/O address translation method for specifying a relaxed ordering for I/O accesses
IBM2 citations62
US7716423B2May 11, 2010
Pseudo LRU algorithm for hint-locking during software and hardware address translation cache miss handling modes
IBM5 citations62
US7472227B2Dec 30, 2008
Invalidating multiple address cache entries
IBM1 citations51
US7539840B2May 26, 2009
Handling concurrent address translation cache misses and hits under those misses while maintaining command order
IBM1 citations47