Inventor

YEH CHIH CHIEH

TW224 patents

⚠️ This page may combine multiple inventors who share the name “YEH CHIH CHIEH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

YEH CHIH CHIEH

TAIWAN SEMICONDUCTOR MFG CO LTD

Threshold voltage adjustment for a gate-all-around semiconductor structure

Strained nanowire CMOS device and method of forming

Multiple gate field-effect transistors having oxygen-scavenged gate stack

Multi-gate device and method of fabrication thereof

Semiconductor device and manufacturing method thereof

Structure and formation method of semiconductor device structure with nanowires

Semiconductor device structure with semiconductor wire

Semiconductor device and manufacturing method thereof

Semiconductor device and method of manufacturing the same

Semiconductor device and method

Semiconductor device and method

Semiconductor device and method of manufacturing the same

Strained nanowire CMOS device and method of forming

Semiconductor device and method

Fin field effect transistor (FinFET) device structure with dummy fin structure and method for forming the same

Multi-gate device and method of fabrication thereof

Multi-gate device and method of fabrication thereof

Method of manufacturing a semiconductor device with multilayered channel structure

Semiconductor device and manufacturing method thereof

MACRONIX INT CO LTD

Nonvolatile semiconductor memory cell with electron-trapping erase state and methods for operating the same

Integrated code and data flash memory

Apparatus and method for programming virtual ground nonvolatile memory cell array without disturbing adjacent cells

Charge trapping non-volatile memory and method for gate-by-gate erase for same

Method and apparatus for operating a string of charge trapping memory cells

NAND-type non-volatile memory cell and method for operating same

Method of programming and erasing multi-level flash memory

Erasing method for non-volatile memory

Memory erase method and device with optimal data retention for nonvolatile memory

Non-volatile memory and operating method thereof

Erase scheme for non-volatile memory

Memory array including multiple-gate charge trapping non-volatile cells

Method and apparatus for operating a non-volatile memory array

Overerase protection of memory cells for nonvolatile memory

Operation methods for a non-volatile memory cell in an array

Method for programming programmable eraseless memory

Method and apparatus for programming nonvolatile memory

Trim circuit and method for tuning a current level of a reference cell in a flash memory

LEE TSUNG-LIN

Strained structure of semiconductor device and method of making the strained structure

Gate structure for semiconductor device

FinFETs with different fin heights

Sacrificial offset protection film for a FinFET device

TAIWAN SEMICONDUCTOR MFG

FinFETs with multiple Fin heights

FinFETs with multiple fin heights

FinFETs with multiple fin heights

YEH CHIH CHIEH

Germanium FinFETs with metal gates and stressors

Accumulation type FinFET, circuits and fabrication method thereof

PERNG TSU-HSIU

Fin-like field effect transistor (FinFET) device and method of manufacturing same

CHANG CHIH-HAO

Method for forming high germanium concentration SiGe stressor

LAI LI-SHYUE

Finfets and methods for forming the same

MACRONIX INTERNAT CO TD

Charge trapping non-volatile memory with two trapping locations per gate, and method for operating same