Inventor
BEYLIN BORIS
US19 patents
⚠️ This page may combine multiple inventors who share the name “BEYLIN BORIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
5 patentsUS6493698B1Dec 10, 2002
String search scheme in a distributed architecture
INTEL CORP94 citations98
US6952694B2Oct 4, 2005
Full regular expression search of network traffic
INTEL CORP76 citations97
US7406470B2Jul 29, 2008
Full regular expression search of network traffic
INTEL CORP45 citations95
US7293020B2Nov 6, 2007
String search scheme in a distributed architecture
INTEL CORP7 citations73
US7917509B2Mar 29, 2011
String search scheme in a distributed architecture
INTEL CORP0 citations52
SAMSUNG ELECTRONICS CO LTD
4 patentsUS10061591B2Aug 28, 2018
Redundancy elimination in single instruction multiple data/thread (SIMD/T) execution processing
SAMSUNG ELECTRONICS CO LTD7 citations79
US9483264B2Nov 1, 2016
Trace-based instruction execution processing
SAMSUNG ELECTRONICS CO LTD3 citations71
US10061592B2Aug 28, 2018
Architecture and execution for efficient mixed precision computations in single instruction multiple data/thread (SIMD/T) devices
SAMSUNG ELECTRONICS CO LTD3 citations70
US9727341B2Aug 8, 2017
Control flow in a thread-based environment without branching
SAMSUNG ELECTRONICS CO LTD1 citations49
SUN MICROSYSTEMS INC
3 patentsUS5903900AMay 11, 1999
Method and apparatus for optimizing exact garbage collection of array nodes in a carded heap
SUN MICROSYSTEMS INC110 citations97
US5930510AJul 27, 1999
Method and apparatus for an improved code optimizer for pipelined computers
SUN MICROSYSTEMS INC57 citations95
US6148302ANov 14, 2000
Method, apparatus, system and computer program product for initializing a data structure at its first active use
SUN MICROSYSTEMS INC38 citations92
NVIDIA CORP
3 patentsUS8381203B1Feb 19, 2013
Insertion of multithreaded execution synchronization points in a software program
NVIDIA CORP55 citations94
US7681187B2Mar 16, 2010
Method and apparatus for register allocation in presence of hardware constraints
NVIDIA CORP47 citations90
US9292269B2Mar 22, 2016
Control flow optimization for efficient program code execution on a processor
NVIDIA CORP0 citations27