Inventor

CAO HAIJING

SG40 patents

⚠️ This page may combine multiple inventors who share the name “CAO HAIJING”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

CAO HAIJING

LIN YAOJIAN

Semiconductor package with semiconductor core structure and method of forming the same

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

Wafer level die integration and method therefor

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Semiconductor device and method of making integrated passive devices

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Semiconductor device with solder bump formed on high topography plated Cu pads

Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit

Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component

Semiconductor device and method of forming passive devices

Semiconductor device and method of forming high-frequency circuit structure and method thereof

Semiconductor device and method of forming vertical interconnect structure in substrate for IPD and baseband circuit separated by high-resistivity molding compound

Semiconductor device and method of forming a fan-out structure with integrated passive device and discrete component

Semiconductor device and method of forming passive devices

Semiconductor device having embedded integrated passive devices electrically interconnected using conductive pillars

Method of forming an inductor on a semiconductor wafer

Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels

Semiconductor device and method of forming an IPD over a high-resistivity encapsulant separated from other IPDS and baseband circuit

Circuit system with circuit element and reference plane

Method for manufacture of integrated circuit package system with protected conductive layers for pads

Integrated circuit system with metal-insulator-metal circuit element

Integrated passive device system

STATS CHIPPAC LTD

Wafer level die integration and method therefor

Semiconductor package with semiconductor core structure and method of forming same

Semiconductor device and method of forming high-frequency circuit structure and method thereof

Semiconductor device and method for forming passive circuit elements with through silicon vias to backside interconnect structures

Semiconductor device and method of forming integrated passive device module

Integrated circuit package system with bump pad

Semiconductor device and method of embedding integrated passive devices into the package electrically interconnected using conductive pillars

Semiconductor device with integrated passive circuit and method of making the same using sacrificial substrate

Method of forming solder bump on high topography plated Cu

Semiconductor device and method of forming shielding layer over integrated passive device using conductive channels

Method of forming an inductor on a semiconductor wafer

Integrated circuit package system with protected conductive layers for pads and method of manufacturing thereof

Method of forming an inductor on a semiconductor wafer

Semiconductor device and method of protecting passivation layer in a solder bump process

Integrated circuit system for bonding

Integrated passive devices

Semiconductor device with solder bump formed on high topography plated Cu pads