Inventor
LEIJTEN JEROEN ANTON JOHAN
NL17 patents
⚠️ This page may combine multiple inventors who share the name “LEIJTEN JEROEN ANTON JOHAN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
KONINKL PHILIPS ELECTRONICS NV
8 patentsUS7231478B2Jun 12, 2007
Programmed access latency in mock multiport memory
KONINKL PHILIPS ELECTRONICS NV52 citations92
US6948158B2Sep 20, 2005
Retargetable compiling system and method
KONINKL PHILIPS ELECTRONICS NV20 citations90
US7313671B2Dec 25, 2007
Processing apparatus, processing method and compiler
KONINKL PHILIPS ELECTRONICS NV8 citations73
US7308540B2Dec 11, 2007
Pseudo multiport data memory has stall facility
KONINKL PHILIPS ELECTRONICS NV7 citations73
US6643738B2Nov 4, 2003
Data processor utilizing set-associative cache memory for stream and non-stream memory addresses
KONINKL PHILIPS ELECTRONICS NV10 citations66
US7082518B2Jul 25, 2006
Interruptible digital signal processor having two instruction sets
KONINKL PHILIPS ELECTRONICS NV4 citations60
US7032102B2Apr 18, 2006
Signal processing device and method for supplying a signal processing result to a plurality of registers
KONINKL PHILIPS ELECTRONICS NV4 citations58
US7302555B2Nov 27, 2007
Zero overhead branching and looping in time stationary processors
KONINKL PHILIPS ELECTRONICS NV0 citations51
LEIJTEN JEROEN ANTON JOHAN
4 patentsUS8095780B2Jan 10, 2012
Register systems and methods for a multi-issue processor
LEIJTEN JEROEN ANTON JOHAN5 citations60
US8145888B2Mar 27, 2012
Data processing circuit with a plurality of instruction modes, method of operating such a data circuit and scheduling method for such a data circuit
LEIJTEN JEROEN ANTON JOHAN2 citations56
US8838945B2Sep 16, 2014
Data processing circuit with a plurality of instruction modes for processing time-stationary encoded instructions, and method of operating/scheduling such data circuit
LEIJTEN JEROEN ANTON JOHAN1 citations45
US9201657B2Dec 1, 2015
Lower power assembler
LEIJTEN JEROEN ANTON JOHAN0 citations39
SILICON HIVE BV
3 patentsUS7574583B2Aug 11, 2009
Processing apparatus including dedicated issue slot for loading immediate value, and processing method therefor
SILICON HIVE BV6 citations60
US7937572B2May 3, 2011
Run-time selection of feed-back connections in a multiple-instruction word processor
SILICON HIVE BV0 citations40
US7873813B2Jan 18, 2011
Variable length VLIW instruction with instruction fetch control bits for prefetching, stalling, or realigning in order to handle padding bits and instructions that cross memory line boundaries
SILICON HIVE BV0 citations40