Inventor

SCHOINAS IOANNIS

US16 patents

⚠️ This page may combine multiple inventors who share the name “SCHOINAS IOANNIS”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

INTEL CORP

13 patents

US7340582B2Mar 4, 2008

Method and apparatus for managing transaction requests in a multi-node architecture

INTEL CORP88 citations97

US7467381B2Dec 16, 2008

Resource partitioning and direct access utilizing hardware support for virtualization

INTEL CORP51 citations92

US7127566B2Oct 24, 2006

Synchronizing memory copy operations with memory accesses

INTEL CORP17 citations92

US7444493B2Oct 28, 2008

Address translation for input/output devices using hierarchical translation tables

INTEL CORP54 citations90

US7433985B2Oct 7, 2008

Conditional and vectored system management interrupts

INTEL CORP36 citations90

US7370135B2May 6, 2008

Band configuration agent for link based computing system

INTEL CORP2 citations58

US9736181B2Aug 15, 2017

Hardening data transmissions against power side channel analysis

INTEL CORP1 citations51

US7257682B2Aug 14, 2007

Synchronizing memory copy operations with memory accesses

INTEL CORP0 citations51

US9390320B2Jul 12, 2016

Performing hand gesture recognition using 2D image data

INTEL CORP1 citations47

MADUKKARUMUKUMANA RAJESH

2 patents

US8706942B2Apr 22, 2014

Direct memory access (DMA) address translation between peer-to-peer input/output (I/O) devices

MADUKKARUMUKUMANA RAJESH4 citations70

US8850098B2Sep 30, 2014

Direct memory access (DMA) address translation between peer input/output (I/O) devices

MADUKKARUMUKUMANA RAJESH3 citations60

SCHOINAS IOANNIS

1 patent

US8843727B2Sep 23, 2014

Performance enhancement of address translation using translation tables covering large address spaces

SCHOINAS IOANNIS9 citations79

SCHOINAS IOANNIS

INTEL CORP

Fault processing for direct memory access address translation

Caching support for direct memory access address translation

Interrupt redirection for virtual partitioning

Performing memory RAS operations over a point-to-point interconnect

Method and apparatus for managing transaction requests in a multi-node architecture

Resource partitioning and direct access utilizing hardware support for virtualization

Synchronizing memory copy operations with memory accesses

Address translation for input/output devices using hierarchical translation tables

Conditional and vectored system management interrupts

Band configuration agent for link based computing system

Hardening data transmissions against power side channel analysis

Synchronizing memory copy operations with memory accesses

Performing hand gesture recognition using 2D image data

MADUKKARUMUKUMANA RAJESH

Direct memory access (DMA) address translation between peer-to-peer input/output (I/O) devices

Direct memory access (DMA) address translation between peer input/output (I/O) devices

SCHOINAS IOANNIS

Performance enhancement of address translation using translation tables covering large address spaces