Inventor

NUZMAN JOSEPH

IL54 patents

⚠️ This page may combine multiple inventors who share the name “NUZMAN JOSEPH”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

NUZMAN JOSEPH

INTEL CORP

Apparatuses, methods, and systems for instructions to compartmentalize code

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses utilizing CPU storage with a memory reference

Hardware apparatuses and methods for memory corruption detection

Memory corruption detection

Multiple chunk support for memory corruption detection architectures

Systems, methods, and apparatuses for heterogeneous computing

Systems, methods, and apparatuses for heterogeneous computing

Memory write protection for memory corruption detection architectures

Method and apparatus for cache line write back operation

Hardware apparatuses and methods for memory corruption detection

Linear memory address transformation and management

Method and apparatus for store durability and ordering in a persistent memory architecture

Systems, methods, and apparatuses for heterogeneous computing

Apparatuses, methods, and systems to precisely monitor memory store accesses

Apparatuses and methods for speculative execution side channel mitigation

Apparatuses, methods, and systems to precisely monitor memory store accesses

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

Spatial and temporal merging of remote atomic operations

Byte level granularity buffer overflow detection for memory corruption detection architectures

Apparatuses and methods for speculative execution side channel mitigation

Apparatuses, methods, and systems for instructions to compartmentalize code

Adaptive hierarchical cache policy in a microprocessor

Apparatuses, methods, and systems toprecisely monitor memory store accesses

Microarchitectural mechanisms for the prevention of side-channel attacks using a thread identification (TID) and a privilege level bit

Spatial and temporal merging of remote atomic operations

Microarchitectural mechanisms for the prevention of side-channel attacks

Enhanced address space layout randomization

Enhanced address space layout randomization

Memory write protection for memory corruption detection architectures

Byte level granularity buffer overflow detection for memory corruption detection architectures

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Restricted speculative execution mode to prevent observable side effects

System, apparatus and method for prefetching physical pages in a processor

Systems and methods for adaptive multipath probability (AMP) prefetcher

Dynamic inclusive last level cache

Circuitry and methods for a conditional fence instruction

Apparatus and method for a range comparison, exchange, and add

Systems, methods, and apparatuses for defending against cross-privilege linear probes

Hardware apparatuses and methods for memory corruption detection

Adaptive hierarchical cache policy in a microprocessor

Systems, methods, and apparatuses to control CPU speculation for the prevention of side-channel attacks

Device, system and method to detect an uninitialized memory read

Memory write protection for memory corruption detection architectures

Pipelined prefetcher for parallel advancement of multiple data streams

Method and apparatus for distributed snoop filtering

Memory tagging apparatus and method

SAGER DAVID J

Systems, apparatuses, and methods for a hardware and software system to automatically decompose a program to multiple parallel threads

SORANI IRIS

Cache memory staged reopen

RAIKIN SHLOMO

Protecting the integrity of binary translated code