Inventor

ESSER STEVEN K

US56 patents

⚠️ This page may combine multiple inventors who share the name “ESSER STEVEN K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

ESSER STEVEN K

IBM

Extracting salient features from video using a neurosynaptic system

Massively parallel neural inference computing elements

Cortical simulator for object-oriented simulation of a neural network

Classifying features using a neurosynaptic system

Scene understanding using a neurosynaptic system

Extracting motion saliency features from video using a neurosynaptic system

Multi-compartment neurons with neural cores

Scene understanding using a neurosynaptic system

Extracting salient features from video using a neurosynaptic system

Feature extraction using a neurosynaptic system for object classification

Scene understanding using a neurosynaptic system

Scene understanding using a neurosynaptic system

Extracting salient features from video using a neurosynaptic system

Scheduler for mapping neural networks onto an array of neural cores in an inference processing unit

Runtime reconfigurable neural network processor core

Reconfigurable and customizable general-purpose circuits for neural networks

Scene understanding using a neurosynaptic system

Classifying features using a neurosynaptic system

Converting spike event data to digital numeric data

Converting digital numeric data to spike event data

Multi-mode low-precision inner-product computation circuits for massively parallel neural inference engine

Scalable neural hardware for the noisy-OR model of Bayesian networks

Reconfigurable and customizable general-purpose circuits for neural networks

Multi-compartment neurons with neural cores

Data representation for dynamic precision in neural network cores

Networks for distributing parameters and data to neural network compute cores

Runtime reconfigurable neural network processor core

Instruction distribution in an array of neural network cores

High dynamic range, high class count, high input rate winner-take-all on neuromorphic hardware

Data distribution in an array of neural network cores

Extracting motion saliency features from video using a neurosynaptic system

Hardware-software co-design of neurosynaptic systems

Massively parallel neural inference computing elements

Converting digital numeric data to spike event data

Block transfer of neuron output values through data memory for neurosynaptic processors

Hierarchical parallelism in a network of distributed neural network cores

Defect resistant designs for location-sensitive neural network processor arrays

Parallel computational architecture with reconfigurable core-level and vector-level parallelism

Scene understanding using a neurosynaptic system

ESSER STEVEN K

Multi-compartment neurons with neural cores

Multi-compartment neurons with neural cores

Canonical spiking neuron network for spatiotemporal associative memory

Canonical spiking neuron network for spatiotemporal associative memory

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

Reconfigurable and customizable general-purpose circuits for neural networks

ARTHUR JOHN V

Integrate and fire electronic neurons

Scalable neural hardware for the noisy-OR model of Bayesian networks

MODHA DHARMENDRA S

Multi-compartment neuron suitable for implementation in a distributed hardware model by reducing communication bandwidth

ANANTHANARAYANAN RAJAGOPAL

Synaptic weight normalized spiking neuronal networks

DATTA PALLAB

Multi-processor cortical simulations with reciprocal connections with shared weights