Inventor

MONTOYE ROBERT K

US85 patents

⚠️ This page may combine multiple inventors who share the name “MONTOYE ROBERT K”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

MONTOYE ROBERT K

IBM

Floating point unit for calculating A=XY+Z having simultaneous multiply and add

Methods and arrangements to adjust a duty cycle

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Limited switch dynamic logic circuit

Methods for caching cache tags

Leading 0/1 anticipator (LZA)

Floating point arithmetic two cycle data flow

Floating point arithmetic two cycle data flow

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

System for SIMD-oriented management of register maps for map-based indirect register-file access

Sectored cache memory

Methods involving memory caches

Controlled load limited switch dynamic logic circuitry

Cache memory system for selectively storing directory information for a higher level cache in portions of a lower level cache

Scannable limited switch dynamic logic (LSDL) circuit

Asymmetrical clock separation and stage delay optimization in single flux quantum logic

Integrated circuit chip package with formable intermediate 3D wiring structure

Limited switch dynamic logic selector circuits

Apparatus for determining if there is a loss of data during a shift operation

Partial decode shifter/rotator

Stacked, reconfigurable co-regulation of processing units for ultra-wide DVFS

Reconfigurable and customizable general-purpose circuits for neural networks

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

High-performance hash joins using memory with extensive internal parallelism

Test circuit for differential cascode voltage switch

High-speed latch circuits by selective use of large gate pitch

Reconfigurable and customizable general-purpose circuits for neural networks

Content addressable memory array

CHANG LELAND

Content addressable memory array programmed to perform logic operations

Time division multiplexed limited switch dynamic logic

Electronic synapses for reinforcement learning

Sense scheme for phase change material content addressable memory

Low voltage signaling

Test structure for characterizing multi-port static random access memory and register file arrays

Time division multiplexed limited switch dynamic logic

Test structure for characterizing multi-port static random access memory and register file arrays

HAL COMPUTER SYSTEMS INC

Apparatus for storing &#34;Don&#39;t Care&#34; in a content addressable memory cell

Method and apparatus for detecting multiple matches in a content addressable memory

Tri state buffer circuit for dual power system

CMOS buffer circuit having increased speed

DENNARD ROBERT H

Switched capacitor voltage converters

Switched capacitor voltage converters

LAM CHUNG H

Multi-bit resistance measurement

Writing scheme for phase change material-content addressable memory

BREITWISCH MATTHEW J

Resistive memory devices having a not-and (NAND) structure

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

GSCHWIND MICHAEL KARL

Implementing instruction set architectures with non-contiguous register file specifiers

ANDRY PAUL STEPHEN

Silicon carrier structure and method of forming same

BLANER BARTHOLOMEW

Shared parallel adder tree for executing multiple different population count operations

Apparatus for storing "Don't Care" in a content addressable memory cell