Inventor

SEO JAE-SUN

US32 patents

⚠️ This page may combine multiple inventors who share the name “SEO JAE-SUN”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

SEO JAE-SUN

IBM

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Reconfigurable and customizable general-purpose circuits for neural networks

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Reconfigurable and customizable general-purpose circuits for neural networks

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Reconfigurable and customizable general-purpose circuits for neural networks

Efficient voltage conversion

Efficient voltage conversion

Reconfigurable switched-capacitor voltage converter circuit, integrated circuit (IC) chip including the circuit and method of switching voltage on chip

UNIV ARIZONA STATE

Memory compression in a deep neural network

Resistive random-access memory for embedded computation

Static random-access memory for deep neural networks

Cascaded computing for convolutional neural networks

Static random-access memory for deep neural networks

Programmable in-memory computing accelerator for low-precision deep neural network inference

SEO JAE SUN

Neuromorphic computational system(s) using resistive synaptic devices

Resistive random-access memory for exclusive NOR (XNOR) neural networks

Cascaded computing for convolutional neural networks

Smart hardware security engine using biometric features and hardware-specific features

Static and dynamic precision adaptation for hardware learning and classification

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

Reconfigurable and customizable general-purpose circuits for neural networks

UNIV COLUMBIA

Circuits and methods for in-memory computing

Circuits and methods for in-memory computing

INTEL CORP

Interconnection scheme for reconfigurable neuromorphic hardware

Method and apparatus for treating a signal

YU SHIMENG

Resistive cross-point architecture for robust data representation with arbitrary precision

SEO JAE-SUN

High-bandwidth on-chip communication

CHEN GREGORY K

Apparatus and method for a digital neuromorphic processor

YIN SHIHUI

Electrocardiographic biometric authentication