Inventor

TIERNO JOSE A

US59 patents

⚠️ This page may combine multiple inventors who share the name “TIERNO JOSE A”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

TIERNO JOSE A

IBM

Methods and apparatus for timing recovery from a sampled and equalized data signal

Phase-locked loop circuits and methods implementing multiplexer circuit for fine tuning control of digitally controlled oscillators

Method and apparatus for efficient implementation of digital filter with thermometer-code-like output

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a universal substrate of adaptation

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Phase-locked loop circuits and methods implementing pulsewidth modulation for fine tuning control of digitally controlled oscillators

Soft error protection in individual memory devices

Error type identification circuit for identifying different types of errors in communications devices

Method and apparatus for reducing latency in a digital signal processing device

Reconfigurable and customizable general-purpose circuits for neural networks

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Methods and apparatus for clock synchronization and data recovery in a receiver

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

Reconfigurable and customizable general-purpose circuits for neural networks

Transimpedance amplifier

Method and circuit for controlling clock frequency of an electronic circuit with noise mitigation

Digital phase and frequency detector

Pseudofooter circuit for dynamic CMOS (Complementary metal-oxide-semiconductor) logic

Method and apparatus for comparing two binary numbers with a power-of-two threshold

Time-division multiplexed neurosynaptic module with implicit memory addressing for implementing a neural network

Data transmission system and method of correcting an error in parallel data paths of a data transmission system

Reconfigurable and customizable general-purpose circuits for neural networks

APPLE INC

Chip to chip interface with scalable bandwidth

Chip to chip interface with scalable bandwidth

Serial data receiver circuit with dither assisted equalization

Data detection on serial communication links

Data detection on serial communication links

Clock frequency limiter

Clock frequency limiter

Encoding and decoding for PAM transmitter and receiver

AINSPAN HERSCHEL A

Hybrid phase-locked loop architectures

Optimal dithering of a digitally controlled oscillator with clock dithering for gain and bandwidth control

Hybrid phase-locked loop architectures

FRIEDMAN DANIEL J

Phase and frequency detector with output proportional to frequency difference

Producing spike-timing dependent plasticity in a neuromorphic network utilizing phase change synaptic devices

BREZZO BERNARD V

Reconfigurable and customizable general-purpose circuits for neural networks

Reconfigurable and customizable general-purpose circuits for neural networks

PROESEL JONATHAN E

Transimpedance amplifier

FRIEDMAN DANIEL

Calibration schemes for charge-recycling stacked voltage domains

SADHU BODHISATWA

Fully decoupled LC-tank based oscillator topology for low phase noise and high oscillation amplitude applications

CALIFORNIA INSTITUE OF TECHNOL

Gallium arsenide source follower FET logic family with diodes for preventing leakage currents

ELAD DANNY

Phase profile generator

ASAAD SAMEH W

Method and infrastructure for cycle-reproducible simulation on large scale digital circuits on a coordinated set of field-programmable gate arrays (FPGAs)

FERRISS MARK

Reducing phase locked loop phase lock time

INTERNAT BSUINESS MACHINES COR

Technique for efficiently managing both short-term and long-term frequency adjustments of an electronic circuit clock signal

FERRISS MARK A

PLL bandwidth correction with offset compensation