Inventor

BAR-ON TOMER

IL58 patents

⚠️ This page may combine multiple inventors who share the name “BAR-ON TOMER”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

BAR-ON TOMER

INTEL CORP

Multiply-accumulate “0” data gating

Low rank matrix compression

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

Engine to enable high speed context switching via on-die storage

Motion biased foveated renderer

Engine to enable high speed context switching via on-die storage

Decoupled multi-layer render frequency

Motion biased foveated renderer

GPU mixed primitive topology type processing

Decouple multi-layer render fequency

On demand MSAA resolve during lens correction and/or other post-processing phases

Motion biased foveated renderer

Real time context dependent deep learning

Low rank matrix compression

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

Storage system of DNN outputs for black box

Multiply-accumulate “0” data gating

Multiply-accumulate “0” data gating

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Real time context dependent deep learning

Compute optimization mechanism for deep neural networks

Scheduling configuration for deep learning networks

Engine to enable high speed context switching via on-die storage

Topology shader technology

Motion biased foveated renderer

Real time context dependent deep learning

Low rank matrix compression

Graphics anti-aliasing resolve with stencil mask

Variable precision and mix type representation of multiple layers in a network

Graphics anti-aliasing resolve with stencil mask

Graphics anti-aliasing resolve with stencil mask

Topology shader technology

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Storage system of DNN outputs for black box

Multiply-accumulate “0” data gating

GPU mixed primitive topology type processing

Sub-graph in frequency domain and dynamic selection of convolution implementation on a GPU

On demand MSAA resolve during lens correction and/or other post-processing phases

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

Topology shader technology

Light field displays having synergistic data formatting, re-projection, foveation, tile binning and image warping technology

Variable precision and mix type representation of multiple layers in a network

Graphics anti-aliasing resolve with stencil mask

Topology shader technology

Scheduling configuration for deep learning networks

Tile-based multiple resolution rendering of images

Memory-based dependency tracking and cache pre-fetch hardware for multi-resolution shading

KOKER ALTUG

Engine to enable high speed context switching via on-die storage

BAR ON TOMER

On demand MSAA resolve during lens correction and/or other post-processing phases

SOLAREDGE TECHNOLOGIES LTD

Drive circuit for regulating voltage and reducing energy consumed