Inventor

PATEL BAIJU

US42 patents

⚠️ This page may combine multiple inventors who share the name “PATEL BAIJU”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.

PATEL BAIJU

INTEL CORP

Cryptographic pointer address encoding

Low overhead integrity protection with high availability for trust domains

Platform security mechanism

Returning to a control transfer instruction

System and method for providing security mechanisms for securing network communication

Mechanism for instruction set based thread execution of a plurality of instruction sequencers

Flexible container attestation

ISA accessible physical unclonable function

Platform security mechanism

Cryptographic memory ownership

Side-channel exploit detection

Composable trustworthy execution environments

Cryptographic pointer address encoding

Obscuring memory access patterns

Storage encryption using converged cryptographic engine

Side-channel exploit detection

System, method and apparatus for total storage encryption

Composable trusted execution environments

Platform security mechanism

Platform security mechanism

Asymmetric device attestation using physically unclonable functions

Platform security mechanism

Encoded inline capabilities

Supporting memory paging in virtualized systems using trust domains

Supporting memory paging in virtualized systems using trust domains

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Methods and apparatuses to provide chiplet binding to a system on a chip platform having a disaggregated architecture

Multi-key cryptographic memory protection

ISA accessible physical unclonable function

ISA accessible physical unclonable function

ISA accessible physical unclonable function

Cryptographic pointer address encoding

Systems, methods, and apparatuses for defending against cross-privilege linear probes

Cryptographic pointer address encoding

Cryptographic pointer address encoding

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

Method, apparatus, system, and computer readable medium for providing apparatus security

Instruction for performing an overload check

Method, apparatus, system, and computer readable medium for providing apparatus security

Memory assisted incline encryption/decryption

WANG HONG

Instruction set architecture-based inter-sequencer communications with a heterogeneous resource

BUXTON MARK

Obscuring memory access patterns