Inventor
LUPON MARC
ES18 patents
⚠️ This page may combine multiple inventors who share the name “LUPON MARC”. Patents are grouped by organization below to help distinguish them — per-person disambiguation is on the roadmap.
INTEL CORP
13 patentsUS9978014B2May 22, 2018
Reconfigurable processing unit
INTEL CORP24 citations91
US9613001B2Apr 4, 2017
Processing device for performing convolution operations
INTEL CORP19 citations91
US9971540B2May 15, 2018
Storage device and method for performing convolution operations
INTEL CORP18 citations83
US9778909B2Oct 3, 2017
Double rounded combined floating-point multiply and add
INTEL CORP7 citations83
US9477441B2Oct 25, 2016
Double rounded combined floating-point multiply and add
INTEL CORP3 citations72
US10002108B2Jun 19, 2018
Processing device for performing convolution operations
INTEL CORP2 citations71
US12032653B2Jul 9, 2024
Method and apparatus for distributed and cooperative computation in artificial neural networks
INTEL CORP0 citations60
US11281965B2Mar 22, 2022
Reconfigurable processing unit
INTEL CORP0 citations60
US10997273B2May 4, 2021
Method and apparatus for distributed and cooperative computation in artificial neural networks
INTEL CORP1 citations60
US9389871B2Jul 12, 2016
Combined floating point multiplier adder with intermediate rounding logic
INTEL CORP0 citations51
US10402468B2Sep 3, 2019
Processing device for performing convolution operations
INTEL CORP0 citations50
US10061587B2Aug 28, 2018
Instruction and logic for bulk register reclamation
INTEL CORP0 citations40
US10157063B2Dec 18, 2018
Instruction and logic for optimization level aware branch prediction
INTEL CORP0 citations36
MARTINEZ RAUL
2 patentsUS9116719B2Aug 25, 2015
Partial commits in dynamic binary translation based systems
MARTINEZ RAUL1 citations50
US10013326B2Jul 3, 2018
Propagating a prefetching profile bit from a prefetch queue to a data cache to indicate that a line was prefetched in response to an instruction within a code region
MARTINEZ RAUL1 citations47