Inventor · disambiguated record
Aamer Jaleel
Also filed as: JALEEL AAMER
24 granted patents·3 pending applications·162 citations·filing 2007–2024
95Inventor score
Top patents by PatentIndex Score
27 records- 0192US7725657B2Dynamic quality of service (QoS) for a shared cacheINTEL CORP·Filed 2007·Granted May 25, 2010·33 cites·17 claims
- 0291US10387319B2Processors, methods, and systems for a configurable spatial accelerator with memory system performance, power reduction, and atomics support featuresINTEL CORP·Filed 2017·Granted Aug 20, 2019·9 cites·10 claims
- 0391US10331583B2Executing distributed memory operations using processing elements connected by distributed channelsINTEL CORP·Filed 2013·Granted Jun 25, 2019·26 cites·21 claims
- 0488US9720730B2Providing an asymmetric multicore processor system transparently to an operating systemGINZBURG BORIS·Filed 2011·Granted Aug 1, 2017·15 cites·20 claims
- 0588US8407421B2Cache spill management techniques using cache spill predictionSTEELY JR SIMON C·Filed 2009·Granted Mar 26, 2013·17 cites·29 claims
- 0687US10102134B2Instruction and logic for run-time evaluation of multiple prefetchersINTEL CORP·Filed 2016·Granted Oct 16, 2018·5 cites·20 claims
- 0785US8347301B2Device, system, and method of scheduling tasks of a multithreaded applicationINTEL CORP·Filed 2008·Granted Jan 1, 2013·15 cites·18 claims
- 0883US8533422B2Instruction prefetching using cache line historySUBRAMANIAM SAMANTIKA·Filed 2010·Granted Sep 10, 2013·11 cites·16 claims
- 0980US9262327B2Signature based hit-predicting cacheSTEELY JR SIMON C·Filed 2012·Granted Feb 16, 2016·6 cites·26 claims
- 1077US9378021B2Instruction and logic for run-time evaluation of multiple prefetchersCHISHTI ZESHAN A·Filed 2014·Granted Jun 28, 2016·4 cites·20 claims
- 1176US8132172B2Thread scheduling on multiprocessor systemsLI WENLONG·Filed 2007·Granted Mar 6, 2012·6 cites·6 claims
- 1272US2025021642A1Implementing hardware-based memory safety for a graphic processing unitNVIDIA CORP·Filed 2024·Application pending·0 cites
- 1371US8769201B2Technique for controlling computing resourcesHASENPLAUGH WILLIAM·Filed 2008·Granted Jul 1, 2014·7 cites·28 claims
- 1470US10853276B2Executing distributed memory operations using processing elements connected by distributed channelsINTEL CORP·Filed 2019·Granted Dec 1, 2020·1 cites·24 claims
- 1570US9792212B2Virtual shared cache mechanism in a processing deviceINTEL CORP·Filed 2014·Granted Oct 17, 2017·2 cites·20 claims
- 1670US8839259B2Thread scheduling on multiprocessor systemsLI WENLONG·Filed 2012·Granted Sep 16, 2014·2 cites·7 claims
- 1768US10284470B2Technologies for network device flow lookup managementINTEL CORP·Filed 2014·Granted May 7, 2019·2 cites·21 claims
- 1866US12321230B2Alias-free tagged error correcting codes for machine memory operationsNVIDIA CORP·Filed 2023·Granted Jun 3, 2025·0 cites·23 claims
- 1965US12135781B2Implementing hardware-based memory safety for a graphic processing unitNVIDIA CORP·Filed 2021·Granted Nov 5, 2024·0 cites·24 claims
- 2062US11513957B2Processor and method implementing a cacheline demote machine instructionINTEL CORP·Filed 2020·Granted Nov 29, 2022·0 cites·20 claims
- 2157US10817425B2Hardware/software co-optimization to improve performance and energy for inter-VM communication for NFVs and other producer-consumer workloadsINTEL CORP·Filed 2014·Granted Oct 27, 2020·0 cites·12 claims
- 2256US8769209B2Method and apparatus for achieving non-inclusive cache performance with inclusive cachesJALEEL AAMER·Filed 2010·Granted Jul 1, 2014·1 cites·19 claims
- 2355US2025190373A1Object-level metadata locatorNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2454US2025190632A1Software/hardware co-design for memory safetyNVIDIA CORP·Filed 2024·Application pending·0 cites
- 2551US11836361B2Implementing compiler-based memory safety for a graphic processing unitNVIDIA CORP·Filed 2021·Granted Dec 5, 2023·0 cites·8 claims
- 2647US9286128B2Processor scheduling with thread performance estimation on cores of different typesINTEL CORP·Filed 2013·Granted Mar 15, 2016·0 cites·20 claims
- 2743US9710380B2Managing shared cache by multi-core processorINTEL CORP·Filed 2013·Granted Jul 18, 2017·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →