Inventor · disambiguated record
Abhijit M. Abhyankar
Also filed as: ABHYANKAR ABHIJIT · ABHYANKAR ABHIJIT M · ABHYANKAR ABHIJIT MUKUND
37 granted patents·1,573 citations·filing 1998–2024
98Inventor score
Top patents by PatentIndex Score
37 records- 0198US6839266B1Memory module with offset data lines and bit line swizzle configurationRAMBUS INC·Filed 2002·Granted Jan 4, 2005·189 cites·12 claims
- 0298US6401167B1High performance cost optimized memoryRAMBUS INC·Filed 1998·Granted Jun 4, 2002·168 cites·67 claims
- 0397US7287119B2Integrated circuit memory device with delayed write command processingRAMBUS INC·Filed 2007·Granted Oct 23, 2007·40 cites·23 claims
- 0497US7197611B2Integrated circuit memory device having write latency functionRAMBUS INC·Filed 2005·Granted Mar 27, 2007·54 cites·27 claims
- 0596US11520508B2High performance, high capacity memory modules and systemsRAMBUS INC·Filed 2020·Granted Dec 6, 2022·4 cites·10 claims
- 0696US6075730AHigh performance cost optimized memory with delayed memory writesRAMBUS INC·Filed 1998·Granted Jun 13, 2000·182 cites·6 claims
- 0795US6868474B2High performance cost optimized memoryRAMBUS INC·Filed 2002·Granted Mar 15, 2005·58 cites·6 claims
- 0894US10223299B2High capacity memory system with improved command-address and chip-select signaling modeRAMBUS INC·Filed 2014·Granted Mar 5, 2019·16 cites·19 claims
- 0994US9298228B1Memory capacity expansion using a memory riserRAMBUS INC·Filed 2015·Granted Mar 29, 2016·28 cites·17 claims
- 1094US6378018B1Memory device and system including a low power interfaceINTEL CORP·Filed 1998·Granted Apr 23, 2002·224 cites·32 claims
- 1193US12511064B2High-performance, high-capacity memory modules and systemsRAMBUS INC·Filed 2024·Granted Dec 30, 2025·1 cites·20 claims
- 1293US10642762B2High capacity memory system with improved command-address and chip-select signaling modeRAMBUS INC·Filed 2019·Granted May 5, 2020·6 cites·20 claims
- 1392US11907555B2High performance, high capacity memory modules and systemsRAMBUS INC·Filed 2022·Granted Feb 20, 2024·1 cites·18 claims
- 1491US6473439B1Method and apparatus for fail-safe resynchronization with minimum latencyRAMBUS INC·Filed 1998·Granted Oct 29, 2002·140 cites·22 claims
- 1590US6949958B2Phase comparator capable of tolerating a non-50% duty-cycle clocksRAMBUS INC·Filed 2002·Granted Sep 27, 2005·52 cites·5 claims
- 1689US7330953B2Memory system having delayed write timingRAMBUS INC·Filed 2007·Granted Feb 12, 2008·11 cites·28 claims
- 1788US11899597B2High capacity memory system with improved command-address and chip-select signaling modeRAMBUS INC·Filed 2022·Granted Feb 13, 2024·1 cites·20 claims
- 1888US10348308B2Clock architecture, including clock mesh fabric, for FPGA, and method of operating sameFLEX LOGIX TECH INC·Filed 2018·Granted Jul 9, 2019·6 cites·16 claims
- 1988US7330952B2Integrated circuit memory device having delayed write timing based on read response timeRAMBUS INC·Filed 2007·Granted Feb 12, 2008·10 cites·28 claims
- 2086US10678459B2High performance, high capacity memory modules and systemsRAMBUS INC·Filed 2016·Granted Jun 9, 2020·3 cites·12 claims
- 2186US10411711B2FPGA having a virtual array of logic tiles, and method of configuring and operating sameFLEX LOGIX TECH INC·Filed 2018·Granted Sep 10, 2019·5 cites·20 claims
- 2286US7288973B2Method and apparatus for fail-safe resynchronization with minimum latencyRAMBUS INC·Filed 2005·Granted Oct 30, 2007·11 cites·22 claims
- 2384US7039782B2Memory system with channel multiplexing of multiple memory devicesRAMBUS INC·Filed 2003·Granted May 2, 2006·32 cites·13 claims
- 2483US6708248B1Memory system with channel multiplexing of multiple memory devicesRAMBUS INC·Filed 1999·Granted Mar 16, 2004·91 cites·12 claims
- 2582US7496709B2Integrated circuit memory device having delayed write timing based on read response timeRAMBUS INC·Filed 2007·Granted Feb 24, 2009·6 cites·50 claims
- 2681US7360050B2Integrated circuit memory device having delayed write capabilityRAMBUS INC·Filed 2007·Granted Apr 15, 2008·6 cites·31 claims
- 2781US6370668B1High speed memory system capable of selectively operating in non-chip-kill and chip-kill modesRAMBUS INC·Filed 1999·Granted Apr 9, 2002·83 cites·51 claims
- 2876US6226757B1Apparatus and method for bus timing compensationRAMBUS INC·Filed 1998·Granted May 1, 2001·76 cites·5 claims
- 2973US6226754B1Apparatus and method for device timing compensationRAMBUS INC·Filed 1998·Granted May 1, 2001·33 cites·29 claims
- 3070US11243897B2High capacity memory system with improved command-address and chip-select signaling modeRAMBUS INC·Filed 2020·Granted Feb 8, 2022·0 cites·20 claims
- 3166US6757789B2Apparatus and method for maximizing information transfers over limited interconnect resourcesRAMBUS INC·Filed 2002·Granted Jun 29, 2004·9 cites·26 claims
- 3263US8019958B2Memory write signaling and methods thereofRAMBUS INC·Filed 2010·Granted Sep 13, 2011·1 cites·24 claims
- 3358US7793039B2Interface for a semiconductor memory device and method for controlling the interfaceRAMBUS INC·Filed 2009·Granted Sep 7, 2010·1 cites·34 claims
- 3456US6347354B1Apparatus and method for maximizing information transfers over limited interconnect resourcesRAMBUS INC·Filed 1998·Granted Feb 12, 2002·25 cites·37 claims
- 3554US10686448B2Clock architecture, including clock mesh fabric for FPGA, and method of operating sameFLEX LOGIX TECH INC·Filed 2019·Granted Jun 16, 2020·0 cites·21 claims
- 3650US8205056B2Memory controller for controlling write signalingBARTH RICHARD M·Filed 2011·Granted Jun 19, 2012·0 cites·21 claims
- 3748US8560797B2Method and apparatus for indicating mask informationBARTH RICHARD M·Filed 2012·Granted Oct 15, 2013·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Abhijit M. Abhyankar files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →