Inventor · disambiguated record
Abraham Mendelson
Also filed as: MENDELSON ABRAHAM · MENDELSON ABRAHAM AVI
18 granted patents·2 pending applications·404 citations·filing 1997–2020
95Inventor score
Top patents by PatentIndex Score
20 records- 0196US8230120B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted Jul 24, 2012·21 cites·28 claims
- 0294US8230119B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2010·Granted Jul 24, 2012·14 cites·3 claims
- 0394US8099523B2PCI express enhancements and extensions including transactions having prefetch parametersAJANOVIC JASMIN·Filed 2011·Granted Jan 17, 2012·16 cites·4 claims
- 0494US7451333B2Coordinating idle state transitions in multi-core processorsINTEL CORP·Filed 2004·Granted Nov 11, 2008·94 cites·29 claims
- 0591US8549183B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2010·Granted Oct 1, 2013·8 cites·22 claims
- 0691US8447888B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted May 21, 2013·8 cites·15 claims
- 0790US8555101B2PCI express enhancements and extensionsAJANOVIC JASMIN·Filed 2011·Granted Oct 8, 2013·7 cites·10 claims
- 0889US8473642B2PCI express enhancements and extensions including device window cachingAJANOVIC JASMIN·Filed 2011·Granted Jun 25, 2013·6 cites·12 claims
- 0988US8793404B2Atomic operationsAJANOVIC JASMIN·Filed 2012·Granted Jul 29, 2014·5 cites·6 claims
- 1086US5930830ASystem and method for concatenating discontiguous memory pagesIBM·Filed 1997·Granted Jul 27, 1999·160 cites·12 claims
- 1184US7251811B2Controlling compatibility levels of binary translations between instruction set architecturesINTEL CORP·Filed 2002·Granted Jul 31, 2007·41 cites·33 claims
- 1262US7047395B2Reordering serial data in a system with parallel processing flowsINTEL CORP·Filed 2001·Granted May 16, 2006·9 cites·27 claims
- 1361US7958510B2Device, system and method of managing a resource requestINTEL CORP·Filed 2005·Granted Jun 7, 2011·2 cites·20 claims
- 1461US7260684B2Trace cache filteringINTEL CORP·Filed 2001·Granted Aug 21, 2007·8 cites·24 claims
- 1557US7412569B2System and method to track changes in memoryINTEL CORP·Filed 2003·Granted Aug 12, 2008·5 cites·51 claims
- 1653US12189762B2Secured speculative execution processorTECHNION RES & DEV FOUNDATION·Filed 2020·Granted Jan 7, 2025·0 cites·17 claims
- 1744US10025896B2Exploiting the scan test interface for reverse engineering of a VLSI deviceTECHNION RES & DEV FOUNDATION·Filed 2016·Granted Jul 17, 2018·0 cites·19 claims
- 1843US2007150663A1Device, system and method of multi-state cache coherence schemeMENDELSON ABRAHAM·Filed 2005·Application pending·0 cites
- 1941US2007022274A1Apparatus, system, and method of predicting and correcting critical pathsROSNER RONI·Filed 2005·Application pending·0 cites
- 2034US11972347B2System and method for emulating quantization noise for a neural networkTECHNION RES & DEV FOUNDATION·Filed 2019·Granted Apr 30, 2024·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →