Inventor · disambiguated record
Abraham Yee
Also filed as: YEE ABRAHAM · YEE ABRAHAM F · YEE ABRAHAM FONG
36 granted patents·10 pending applications·689 citations·filing 1990–2014
97Inventor score
Top patents by PatentIndex Score
46 records- 0197US8618651B1Buried TSVs used for decapsNVIDIA CORP·Filed 2012·Granted Dec 31, 2013·34 cites·15 claims
- 0291US5917207AProgrammable polysilicon gate array base cell architectureLSI LOGIC CORP·Filed 1997·Granted Jun 29, 1999·135 cites·20 claims
- 0389US5721151AMethod of fabricating a gate array integrated circuit including interconnectable macro-arraysLSI LOGIC CORP·Filed 1995·Granted Feb 24, 1998·86 cites·13 claims
- 0486US5723896AIntegrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrateLSI LOGIC CORP·Filed 1996·Granted Mar 3, 1998·72 cites·12 claims
- 0583US7964422B1Method and system for controlling a semiconductor fabrication processNVIDIA CORP·Filed 2005·Granted Jun 21, 2011·7 cites·20 claims
- 0682US5220192ARadiation hardened CMOS structure using an implanted P guard structure and method for the manufacture thereofLSI LOGIC·Filed 1992·Granted Jun 15, 1993·66 cites·12 claims
- 0780US5777383ASemiconductor chip package with interconnect layers and routing and testing methodsLSI LOGIC CORP·Filed 1996·Granted Jul 7, 1998·70 cites·10 claims
- 0877US9831184B2Buried TSVs used for decapsNVIDIA CORP·Filed 2013·Granted Nov 28, 2017·3 cites·8 claims
- 0977US9728481B2System with a high power chip and a low power chip having low interconnect parasiticsYEE ABRAHAM F·Filed 2011·Granted Aug 8, 2017·6 cites·10 claims
- 1072US9530714B2Low-profile chip package with modified heat spreaderNVIDIA CORP·Filed 2012·Granted Dec 27, 2016·3 cites·27 claims
- 1170US10032692B2Semiconductor package structureNVIDIA CORP·Filed 2013·Granted Jul 24, 2018·3 cites·12 claims
- 1270US9716051B2Open solder mask and or dielectric to increase lid or ring thickness and contact area to improve package coplanarityNVIDIA CORP·Filed 2012·Granted Jul 25, 2017·2 cites·20 claims
- 1367US5622882AMethod of making a CMOS dynamic random-access memory (DRAM)LSI LOGIC CORP·Filed 1994·Granted Apr 22, 1997·25 cites·20 claims
- 1465US9368422B2Absorbing excess under-fill flow with a solder trenchNVIDIA CORP·Filed 2012·Granted Jun 14, 2016·2 cites·15 claims
- 1557US5593918ATechniques for forming superconductive linesLSI LOGIC CORP·Filed 1994·Granted Jan 14, 1997·20 cites·4 claims
- 1656US9570284B1Method and system for controlling a semiconductor fabrication processYEE ABRAHAM F·Filed 2009·Granted Feb 14, 2017·0 cites·13 claims
- 1754US5358886AMethod of making integrated circuit structure with programmable conductive electrode/interconnect materialLSI LOGIC CORP·Filed 1993·Granted Oct 25, 1994·24 cites·19 claims
- 1853US5508211AMethod of making integrated circuit structure with vertical isolation from single crystal substrate comprising isolation layer formed by implantation and annealing of noble gas atoms in substrateLSI LOGIC CORP·Filed 1994·Granted Apr 16, 1996·19 cites·12 claims
- 1952US5679598AMethod of making a CMOS dynamic random-access memory (DRAM)LSI LOGIC CORP·Filed 1994·Granted Oct 21, 1997·14 cites·19 claims
- 2050US10219387B2Process for manufacturing a printed circuit board having high density microvias formed in a thick substrateNVIDIA CORP·Filed 2013·Granted Feb 26, 2019·0 cites·22 claims
- 2150US5516731AHigh-temperature bias anneal of integrated circuits for improved radiation hardness and hot electron resistanceLSI LOGIC CORP·Filed 1994·Granted May 14, 1996·21 cites·12 claims
- 2247US5538907AMethod for forming a CMOS integrated circuit with electrostatic discharge protectionLSI LOGIC CORP·Filed 1994·Granted Jul 23, 1996·11 cites·6 claims
- 2346US9659815B2System, method, and computer program product for a cavity package-on-package structureNVIDIA CORP·Filed 2014·Granted May 23, 2017·0 cites·20 claims
- 2445US5874754AMicroelectronic cells with bent gates and compressed minimum spacings, and method of patterning interconnections for the gatesLSI LOGIC CORP·Filed 1995·Granted Feb 23, 1999·11 cites·26 claims
- 2544US10096534B2Thermal performance of logic chip in a package-on-package structureNVIDIA CORP·Filed 2012·Granted Oct 9, 2018·0 cites·20 claims
- 2644US9760132B2Stiffening electronic packages by disposing a stiffener ring between substrate center area and conductive padNVIDIA CORP·Filed 2013·Granted Sep 12, 2017·0 cites·30 claims
- 2744US5691218AMethod of fabricating a programmable polysilicon gate array base cell structureLSI LOGIC CORP·Filed 1996·Granted Nov 25, 1997·11 cites·8 claims
- 2843US9379202B2Decoupling capacitors for interposersNVIDIA CORP·Filed 2012·Granted Jun 28, 2016·0 cites·24 claims
- 2943US2014339705A1Iintegrated circuit package using silicon-on-oxide interposer substrate with through-silicon viasNVIDIA CORP·Filed 2013·Application pending·0 cites
- 3043US2014339706A1Integrated circuit package with an interposer formed from a reusable carrier substrateNVIDIA CORP·Filed 2013·Application pending·0 cites
- 3142US2014138815A1Server processing moduleNVIDIA CORP·Filed 2012·Application pending·0 cites
- 3241US6093936AIntegrated circuit with isolation of field oxidation by noble gas implantationLSI LOGIC CORP·Filed 1997·Granted Jul 25, 2000·9 cites·5 claims
- 3341US5561319AIntegrated circuit structure including CMOS devices protected by patterned nitride passivation and method for the fabrication thereofLSI LOGIC CORP·Filed 1994·Granted Oct 1, 1996·12 cites·25 claims
- 3441US2013277855A1High density 3d packageKANG TERRY TECKGYU·Filed 2012·Application pending·0 cites
- 3541US2014151892A1Three dimensional through-silicon via constructionNVIDIA CORP·Filed 2012·Application pending·0 cites
- 3639US2014124254A1Non-solder mask defined copper pad and embedded copper pad to reduce packaging system heightNVIDIA CORP·Filed 2012·Application pending·0 cites
- 3738US5644143AMethod for protecting a semiconductor device with a superconductive lineLSI LOGIC CORP·Filed 1995·Granted Jul 1, 1997·6 cites·7 claims
- 3838US5440154ANon-rectangular MOS device configurations for gate array type integrated circuitsLSI LOGIC CORP·Filed 1993·Granted Aug 8, 1995·6 cites·14 claims
- 3938US2014133105A1Method of embedding cpu/gpu/logic chip into a substrate of a package-on-package structureNVIDIA CORP·Filed 2012·Application pending·0 cites
- 4037US9087830B2System, method, and computer program product for affixing a post to a substrate padZHANG LEILEI·Filed 2012·Granted Jul 21, 2015·0 cites·13 claims
- 4135US5796130ANon-rectangular MOS device configurations for gate array type integrated circuitsLSI LOGIC CORP·Filed 1995·Granted Aug 18, 1998·4 cites·10 claims
- 4235US2013251967A1System, method, and computer program product for controlling warping of a substrateZHANG LEILEI·Filed 2012·Application pending·0 cites
- 4334US2013256873A1System, method, and computer program product for preparing a substrate postZHANG LEILEI·Filed 2012·Application pending·0 cites
- 4433US5648290AMethod of making a CMOS dynamic random-access memory (DRAM)LSI LOGIC CORP·Filed 1994·Granted Jul 15, 1997·4 cites·8 claims
- 4533US2014175619A1Stripline and reference plane implementation for interposers using an implant layerNVIDIA CORP·Filed 2012·Application pending·0 cites
- 4630US5235202ARadiation hardened field dielectric utilizing BPSGLSI LOGIC CORP·Filed 1990·Granted Aug 10, 1993·3 cites·10 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →