Inventor · disambiguated record
Adam Kablanian
Also filed as: KABLANIAN ADAM · KABLANIAN ADAM ALEKSAN
16 granted patents·1 pending application·716 citations·filing 1994–2015
95Inventor score
Top patents by PatentIndex Score
17 records- 0193US5577050AMethod and apparatus for configurable build-in self-repairing of ASIC memories designLSI LOGIC CORP·Filed 1994·Granted Nov 19, 1996·156 cites·17 claims
- 0292US5764878ABuilt-in self repair system for embedded memoriesLSI LOGIC CORP·Filed 1996·Granted Jun 9, 1998·138 cites·13 claims
- 0391US6711067B1System and method for bit line sharingVIRAGE LOGIC CORP·Filed 2002·Granted Mar 23, 2004·63 cites·22 claims
- 0488US8902672B2Methods and apparatus for designing and constructing multi-port memory circuitsIYER SUNDAR·Filed 2013·Granted Dec 2, 2014·13 cites·7 claims
- 0587US6392957B1Fast read/write cycle memory device having a self-timed read/write control circuitVIRAGE LOGIC CORP·Filed 2000·Granted May 21, 2002·47 cites·24 claims
- 0685US6104663AMemory array with a simultaneous read or simultaneous write portsVIRAGE LOGIC CORP·Filed 1999·Granted Aug 15, 2000·61 cites·18 claims
- 0785US6091620AMulti-bank memory with word-line banking, bit-line banking and I/O multiplexing utilizing tilable interconnectsVIRAGE LOGIC CORP·Filed 1999·Granted Jul 18, 2000·53 cites·27 claims
- 0882US6738279B1Multi-bank memory with word-line banking, bit-line banking and I/O multiplexing utilizing tilable interconnectsVIRAGE LOGIC CORP·Filed 2001·Granted May 18, 2004·33 cites·19 claims
- 0980US6065134AMethod for repairing an ASIC memory with redundancy row and input/output linesLSI LOGIC CORP·Filed 1998·Granted May 16, 2000·52 cites·8 claims
- 1075US6310817B1Multi-bank memory with word-line banking, bit-line banking and I/O multiplexing utilizing tilable interconnectsVIRAGE LOGIC CORP·Filed 2000·Granted Oct 30, 2001·20 cites·16 claims
- 1173US9058860B2Methods and apparatus for synthesizing multi-port memory circuitsIYER SUNDAR·Filed 2012·Granted Jun 16, 2015·4 cites·12 claims
- 1267US6587364B1System and method for increasing performance in a compilable read-only memory (ROM)VIRAGE LOGIC CORP·Filed 2002·Granted Jul 1, 2003·13 cites·21 claims
- 1362US6084819AMulti-bank memory with word-line bankingVIRAGE LOGIC CORP·Filed 1999·Granted Jul 4, 2000·21 cites·16 claims
- 1461US6424556B1System and method for increasing performance in a compilable read-only memory (ROM)VIRAGE LOGIC CORP·Filed 2000·Granted Jul 23, 2002·10 cites·16 claims
- 1556US9390212B2Methods and apparatus for synthesizing multi-port memory circuitsCISCO TECH INC·Filed 2015·Granted Jul 12, 2016·1 cites·15 claims
- 1651US6051031AModule-based logic architecture and design flow for VLSI implementationVIRAGE LOGIC CORP·Filed 1997·Granted Apr 18, 2000·31 cites·74 claims
- 1734US2014104960A1Methods and Apparatus for Designing and Constructing High-Speed Memory CircuitsIYER SUNDAR·Filed 2012·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Adam Kablanian files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →