Inventor · disambiguated record
Adam G. Kimura
Also filed as: KIMURA ADAM · KIMURA ADAM G · KIMURA ADAM GAKUTO
6 granted patents·8 pending applications·6 citations·filing 2020–2025
74Inventor score
Files withBATTELLE MEMORIAL INSTITUTE14
Top patents by PatentIndex Score
14 records- 0195US11010519B2Behavioral design recovery from flattened netlistBATTELLE MEMORIAL INSTITUTE·Filed 2020·Granted May 18, 2021·4 cites·20 claims
- 0283US11907627B2Fabricated layout correlationBATTELLE MEMORIAL INSTITUTE·Filed 2021·Granted Feb 20, 2024·2 cites·19 claims
- 0382US12229482B2Recovery of a hierarchical functional representation of an integrated circuitBATTELLE MEMORIAL INSTITUTE·Filed 2023·Granted Feb 18, 2025·0 cites·7 claims
- 0476US2025165686A1Recovery of a hierarchical functional representation of an integrated circuitBATTELLE MEMORIAL INSTITUTE·Filed 2025·Application pending·0 cites
- 0572US12260160B2Fabricated layout correlationBATTELLE MEMORIAL INSTITUTE·Filed 2024·Granted Mar 25, 2025·0 cites·20 claims
- 0669US11651126B2Recovery of a hierarchical functional representation of an integrated circuitBATTELLE MEMORIAL INSTITUTE·Filed 2021·Granted May 16, 2023·0 cites·14 claims
- 0767US2025199061A1Method of Identifying Vulnerable Regions in an Integrated CircuitBATTELLE MEMORIAL INSTITUTE·Filed 2025·Application pending·0 cites
- 0867US2025209243A1Design to fabricated layout correlationBATTELLE MEMORIAL INSTITUTE·Filed 2025·Application pending·0 cites
- 0963US12298343B2Method of identifying vulnerable regions in an integrated circuitBATTELLE MEMORIAL INSTITUTE·Filed 2021·Granted May 13, 2025·0 cites·19 claims
- 1056US2025378253A1System and method for post-silicon analog design verification and validationBATTELLE MEMORIAL INSTITUTE·Filed 2025·Application pending·0 cites
- 1153US2025342303A1Asic design flow and obsolescence recovery through open-source tools and application of drc rules on post-silicon layoutsBATTELLE MEMORIAL INSTITUTE·Filed 2025·Application pending·0 cites
- 1251US2023377127A1Non-destructive verification of integrated circuitsBATTELLE MEMORIAL INSTITUTE·Filed 2023·Application pending·0 cites
- 1344US2023298159A1Integrated circuit layout extraction using parallelized tile image processingBATTELLE MEMORIAL INSTITUTE·Filed 2023·Application pending·0 cites
- 1442US2023017484A1Automated circuit design validationBATTELLE MEMORIAL INSTITUTE·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →