Inventor · disambiguated record
Adam P. Matheny
Also filed as: MATHENY ADAM · MATHENY ADAM P
28 granted patents·2 pending applications·66 citations·filing 2004–2021
94Inventor score
Technology areasG06F
Top patents by PatentIndex Score
30 records- 0192US7581201B2System and method for sign-off timing closure of a VLSI chipIBM·Filed 2007·Granted Aug 25, 2009·35 cites·19 claims
- 0284US9886541B2Process for improving capacitance extraction performanceIBM·Filed 2015·Granted Feb 6, 2018·4 cites·20 claims
- 0381US10360338B2Method for improving capacitance extraction performance by approximating the effect of distant shapesIBM·Filed 2016·Granted Jul 23, 2019·5 cites·9 claims
- 0476US9934341B2Simulation of modifications to microprocessor designIBM·Filed 2015·Granted Apr 3, 2018·2 cites·10 claims
- 0574US11341311B1Generation and selection of universally routable via mesh specifications in an integrated circuitIBM·Filed 2021·Granted May 24, 2022·1 cites·20 claims
- 0673US11176301B2Noise impact on function (NIOF) reduction for integrated circuit designIBM·Filed 2019·Granted Nov 16, 2021·1 cites·20 claims
- 0772US10831938B1Parallel power down processing of integrated circuit designIBM·Filed 2019·Granted Nov 10, 2020·1 cites·17 claims
- 0871US10885243B1Logic partition reporting for integrated circuit designIBM·Filed 2019·Granted Jan 5, 2021·1 cites·17 claims
- 0971US10831953B1Logic partition identifiers for integrated circuit designIBM·Filed 2019·Granted Nov 10, 2020·1 cites·20 claims
- 1069US10878152B1Single-bit latch optimization for integrated circuit (IC) designIBM·Filed 2019·Granted Dec 29, 2020·1 cites·20 claims
- 1167US9785735B1Parallel incremental global routingIBM·Filed 2016·Granted Oct 10, 2017·1 cites·20 claims
- 1266US9858383B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2015·Granted Jan 2, 2018·1 cites·20 claims
- 1363US9223918B2Reducing repeater powerKARTSCHOKE PAUL D·Filed 2012·Granted Dec 29, 2015·2 cites·14 claims
- 1461US6958545B2Method for reducing wiring congestion in a VLSI chip designIBM·Filed 2004·Granted Oct 25, 2005·8 cites·11 claims
- 1558US7904861B2Method, system, and computer program product for coupled noise timing violation avoidance in detailed routingIBM·Filed 2007·Granted Mar 8, 2011·2 cites·14 claims
- 1657US11030376B2Net routing for integrated circuit (IC) designIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 1754US10943040B1Clock gating latch placementIBM·Filed 2019·Granted Mar 9, 2021·0 cites·20 claims
- 1854US9256705B2Reducing repeater powerIBM·Filed 2013·Granted Feb 9, 2016·0 cites·6 claims
- 1953US10354041B2Process for improving capacitance extraction performanceIBM·Filed 2017·Granted Jul 16, 2019·0 cites·1 claims
- 2053US10169526B2Incremental parasitic extraction for coupled timing and power optimizationIBM·Filed 2017·Granted Jan 1, 2019·0 cites·20 claims
- 2153US9928322B2Simulation of modifications to microprocessor designIBM·Filed 2016·Granted Mar 27, 2018·0 cites·18 claims
- 2251US11875099B2Noise impact on function (NIOF) reduction for integrated circuit designIBM·Filed 2021·Granted Jan 16, 2024·0 cites·20 claims
- 2350US10831966B1Multi-fanout latch placement optimization for integrated circuit (IC) designIBM·Filed 2019·Granted Nov 10, 2020·0 cites·20 claims
- 2449US11941340B2Cross-hierarchy antenna condition verificationIBM·Filed 2021·Granted Mar 26, 2024·0 cites·20 claims
- 2548US8032851B2Structure for an integrated circuit design for reducing coupling between wires of an electronic circuitIBM·Filed 2007·Granted Oct 4, 2011·0 cites·10 claims
- 2645US10169516B2Methods and computer program products for via capacitance extractionIBM·Filed 2015·Granted Jan 1, 2019·0 cites·20 claims
- 2745US8006208B2Reducing coupling between wires of an electronic circuitIBM·Filed 2010·Granted Aug 23, 2011·0 cites·19 claims
- 2841US2019362043A1Dynamic update of macro timing models during higher-level timing analysisIBM·Filed 2018·Application pending·0 cites
- 2941US2008148213A1Routing method for reducing coupling between wires of an electronic circuitBELAIDI MOUSSADEK·Filed 2007·Application pending·0 cites
- 3037US10331840B2Resource aware method for optimizing wires for slew, slack, or noiseIBM·Filed 2016·Granted Jun 25, 2019·0 cites·19 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →