Inventor · disambiguated record
Adrian Montero
Also filed as: MONTERO ADRIAN
10 granted patents·4 pending applications·12 citations·filing 2016–2025
80Inventor score
Technology areasG06F
Top patents by PatentIndex Score
14 records- 0195US11442863B2Data processing apparatus and method for generating prefetchesADVANCED RISC MACH LTD·Filed 2020·Granted Sep 13, 2022·8 cites·21 claims
- 0288US11385896B2Determining prefetch patterns with discontinuous stridesADVANCED RISC MACH LTD·Filed 2020·Granted Jul 12, 2022·3 cites·14 claims
- 0372US12367157B2Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devicesQUALCOMM INC·Filed 2024·Granted Jul 22, 2025·0 cites·17 claims
- 0470US12455832B1Compressing data portions in a translation lookaside bufferQUALCOMM INC·Filed 2024·Granted Oct 28, 2025·0 cites·19 claims
- 0570US12130751B2Compressing translation lookaside buffer (TLB) tags using a TLB metadata buffer in processor-based devicesQUALCOMM INC·Filed 2023·Granted Oct 29, 2024·0 cites·20 claims
- 0670US2024273035A1Exploiting virtual address (va) spatial locality using translation lookaside buffer (tlb) entry compression in processor-based devicesQUALCOMM INC·Filed 2024·Application pending·0 cites
- 0770US2025335369A1Compressing data portions in a translation lookaside bufferQUALCOMM INC·Filed 2025·Application pending·0 cites
- 0869US12135652B2Filtering remote data synchronization barrier (DSB) instruction execution in processor-based devicesQUALCOMM INC·Filed 2023·Granted Nov 5, 2024·0 cites·35 claims
- 0965US10102143B2Eviction control for an address translation cacheADVANCED RISC MACH LTD·Filed 2016·Granted Oct 16, 2018·1 cites·18 claims
- 1065US2024273033A1Exploiting virtual address (va) spatial locality using translation lookaside buffer (tlb) entry compression in processor-based devicesQUALCOMM INC·Filed 2023·Application pending·0 cites
- 1153US11914524B2Latency management in synchronization eventsQUALCOMM INC·Filed 2022·Granted Feb 27, 2024·0 cites·19 claims
- 1251US10776043B2Storage circuitry request trackingADVANCED RISC MACH LTD·Filed 2018·Granted Sep 15, 2020·0 cites·14 claims
- 1348US10810126B2Cache storage techniquesADVANCED RISC MACH LTD·Filed 2018·Granted Oct 20, 2020·0 cites·12 claims
- 1445US2023064603A1System and methods for invalidating translation information in cachesNUVIA INC·Filed 2022·Application pending·0 cites
Join the waitlist — get patent alerts
Get an alert when Adrian Montero files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →