Inventor · disambiguated record
Adarsh Panikkar
Also filed as: PANIKKAR ADARSH
9 granted patents·2 pending applications·82 citations·filing 2003–2008
87Inventor score
Top patents by PatentIndex Score
11 records- 0180US7369634B2Training pattern for a biased clock recovery tracking loopINTEL CORP·Filed 2004·Granted May 6, 2008·27 cites·13 claims
- 0270US8098783B2Training pattern for a biased clock recovery tracking loopPANIKKAR ADARSH·Filed 2008·Granted Jan 17, 2012·5 cites·11 claims
- 0369US7500131B2Training pattern based de-skew mechanism and frame alignmentINTEL CORP·Filed 2004·Granted Mar 3, 2009·17 cites·24 claims
- 0469US7466723B2Various methods and apparatuses for lane to lane deskewingINTEL CORP·Filed 2004·Granted Dec 16, 2008·15 cites·13 claims
- 0564US7656983B2Dual clock domain deskew circuitINTEL CORP·Filed 2006·Granted Feb 2, 2010·3 cites·14 claims
- 0653US7346795B2Delaying lanes in order to align all lanes crossing between two clock domainsINTEL CORP·Filed 2004·Granted Mar 18, 2008·5 cites·13 claims
- 0752US7009431B2Interpolator linearity testing systemINTEL CORP·Filed 2004·Granted Mar 7, 2006·7 cites·20 claims
- 0844US7672335B2Non-integer word size translation through rotation of different buffer alignment channelsINTEL CORP·Filed 2003·Granted Mar 2, 2010·0 cites·29 claims
- 0944US7043392B2Interpolator testing systemINTEL CORP·Filed 2004·Granted May 9, 2006·3 cites·43 claims
- 1041US2008130815A1Selective tracking of serial communication link dataKUMAR S REJI·Filed 2006·Application pending·0 cites
- 1138US2006146967A1Keep-out asynchronous clock alignment schemePANIKKAR ADARSH·Filed 2004·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →