Inventor · disambiguated record
Ahsanur Rahman
Also filed as: RAHMAN AHSANUR
8 granted patents·2 pending applications·37 citations·filing 2005–2025
80Inventor score
Top patents by PatentIndex Score
10 records- 0191US7272041B2Memory array with pseudo single bit memory cell and methodINTEL CORP·Filed 2005·Granted Sep 18, 2007·26 cites·23 claims
- 0277US2025322876A1Split block array for 3d nand memoryIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 0375US2025308602A1Independent Multi-Page Read Operation Enhancement TechnologyIntel NDTM US LLC·Filed 2025·Application pending·0 cites
- 0474US7525840B2Memory array with pseudo single bit memory cell and methodINTEL CORP·Filed 2007·Granted Apr 28, 2009·8 cites·4 claims
- 0562US12394497B2Efficient bitline stabilization for program inhibit in NAND arraysIntel NDTM US LLC·Filed 2023·Granted Aug 19, 2025·0 cites·18 claims
- 0660US12340845B2Split block array for 3D NAND memoryIntel NDTM US LLC·Filed 2021·Granted Jun 24, 2025·0 cites·12 claims
- 0757US12334136B2Independent multi-page read operation enhancement technologyIntel NDTM US LLC·Filed 2021·Granted Jun 17, 2025·0 cites·20 claims
- 0853US7551489B2Multi-level memory cell sensingINTEL CORP·Filed 2005·Granted Jun 23, 2009·3 cites·7 claims
- 0952US12315567B2Grouped global wordline driver with shared bias schemeIntel NDTM US LLC·Filed 2021·Granted May 27, 2025·0 cites·16 claims
- 1045US12394492B2Memory cell sensing circuit with adjusted bias from pre-boost operationIntel NDTM US LLC·Filed 2020·Granted Aug 19, 2025·0 cites·22 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →