Inventor · disambiguated record
Akiyo Iwashina
Also filed as: IWASHINA AKIYO
4 granted patents·1 pending application·4 citations·filing 2018–2023
61Inventor score
Files withIBM5
Top patents by PatentIndex Score
5 records- 0180US10490273B1Linearly weight updatable CMOS synaptic array without cell location dependenceIBM·Filed 2018·Granted Nov 26, 2019·4 cites·20 claims
- 0271US2024020522A1Performance and area efficient synapse memory cell structureIBM·Filed 2023·Application pending·0 cites
- 0360US11809982B2Performance and area efficient synapse memory cell structureIBM·Filed 2020·Granted Nov 7, 2023·0 cites·16 claims
- 0456US11087811B1NVM synaptic element with gradual reset capabilityIBM·Filed 2020·Granted Aug 10, 2021·0 cites·25 claims
- 0550US10672471B2Linearly weight updatable CMOS synaptic array without cell location dependenceIBM·Filed 2019·Granted Jun 2, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →