Inventor · disambiguated record
Akshay K. Pathak
Also filed as: PATHAK AKSHAY · PATHAK AKSHAY K · PATHAK AKSHAY KUMAR
12 granted patents·45 citations·filing 2006–2021
87Inventor score
Top patents by PatentIndex Score
12 records- 0192US10848140B1Method and system for detecting clock failureNXP USA INC·Filed 2020·Granted Nov 24, 2020·7 cites·20 claims
- 0289US9190989B1Integrated circuit power managementSHARDA GARIMA·Filed 2014·Granted Nov 17, 2015·11 cites·15 claims
- 0383US11768963B2System and method for validating trust provisioning operation on system-on-chipNXP USA INC·Filed 2021·Granted Sep 26, 2023·2 cites·20 claims
- 0482US7478183B2Method and system for n dimension arbitration algorithm—scalable to any number of end pointsCISCO TECH INC·Filed 2006·Granted Jan 13, 2009·17 cites·20 claims
- 0577US9476937B2Debug circuit for an integrated circuitSHARDA GARIMA·Filed 2014·Granted Oct 25, 2016·4 cites·20 claims
- 0663US9494969B2Reset circuitry for integrated circuitGUPTA ANIRUDDHA·Filed 2014·Granted Nov 15, 2016·2 cites·11 claims
- 0761US9395797B2Microcontroller with multiple power modesSHARDA GARIMA·Filed 2014·Granted Jul 19, 2016·1 cites·21 claims
- 0856US9509305B2Power gating techniques with smooth transitionFREESCALE SEMICONDUCTOR INC·Filed 2014·Granted Nov 29, 2016·1 cites·20 claims
- 0952US11556394B2System and method for controlling access to shared resource in system-on-chipsNXP BV·Filed 2021·Granted Jan 17, 2023·0 cites·20 claims
- 1046US8887017B2Processor switchable between test and debug modesFREESCALE SEMICONDUCTOR INC·Filed 2012·Granted Nov 11, 2014·0 cites·14 claims
- 1140US11177015B2Built-in self-testing and failure correction circuitryNXP USA INC·Filed 2019·Granted Nov 16, 2021·0 cites·20 claims
- 1239US11307767B1System for controlling memory operations in system-on-chipsNXP USA INC·Filed 2020·Granted Apr 19, 2022·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →