Inventor · disambiguated record
Albert M. Chu
Also filed as: CHU ALBERT · CHU ALBERT M · CHU ALBERT MANHEE
87 granted patents·136 pending applications·1,053 citations·filing 1987–2024
99Inventor score
Top patents by PatentIndex Score
223 records- 0199US9680473B1Ultra dense vertical transport FET circuitsIBM·Filed 2016·Granted Jun 13, 2017·79 cites·18 claims
- 0298US9859898B1High density vertical field effect transistor multiplexerIBM·Filed 2016·Granted Jan 2, 2018·23 cites·13 claims
- 0398US9761712B1Vertical transistors with merged active area regionsIBM·Filed 2016·Granted Sep 12, 2017·26 cites·23 claims
- 0497US10074570B23D vertical FET with top and bottom gate contactsIBM·Filed 2017·Granted Sep 11, 2018·16 cites·20 claims
- 0597US7503020B2IC layout optimization to improve yieldIBM·Filed 2006·Granted Mar 10, 2009·110 cites·15 claims
- 0697US6100733AClock latency compensation circuit for DDR timingSIEMENS AG·Filed 1998·Granted Aug 8, 2000·177 cites·1 claims
- 0796US9735029B1Metal fill optimization for self-aligned double patterningIBM·Filed 2016·Granted Aug 15, 2017·22 cites·9 claims
- 0895US12419024B2High density static random-access memoryIBM·Filed 2022·Granted Sep 16, 2025·2 cites·17 claims
- 0995US12328859B2Stacked FET SRAMIBM·Filed 2022·Granted Jun 10, 2025·2 cites·20 claims
- 1095US9052356B2Embedded photon emission calibration (EPEC)CHU ALBERT M·Filed 2012·Granted Jun 9, 2015·25 cites·24 claims
- 1195US4812688ATransistor delay circuitsIBM·Filed 1987·Granted Mar 14, 1989·117 cites·23 claims
- 1294US9954529B2Ultra dense vertical transport FET circuitsIBM·Filed 2017·Granted Apr 24, 2018·9 cites·12 claims
- 1393US12268031B2Backside power rails and power distribution network for density scalingIBM·Filed 2021·Granted Apr 1, 2025·2 cites·12 claims
- 1491US11658116B2Interconnects on multiple sides of a semiconductor structureIBM·Filed 2021·Granted May 23, 2023·2 cites·8 claims
- 1591US8576526B2Reduced current leakage in RC ESD clampsCHU ALBERT M·Filed 2012·Granted Nov 5, 2013·10 cites·18 claims
- 1690US9202554B2Methods and circuits for generating physically unclonable functionIBM·Filed 2014·Granted Dec 1, 2015·13 cites·16 claims
- 1790US6025744AGlitch free delay line multiplexing techniqueIBM·Filed 1998·Granted Feb 15, 2000·76 cites·16 claims
- 1889US8519772B2Alternate power gating enablementCHU ALBERT M·Filed 2011·Granted Aug 27, 2013·10 cites·18 claims
- 1987US6229364B1Frequency range trimming for a delay lineINFINEON TECHNOLOGIES CORP·Filed 1999·Granted May 8, 2001·54 cites·24 claims
- 2086US10755969B2Multi-patterning techniques for fabricating an array of metal lines with different widthsIBM·Filed 2018·Granted Aug 25, 2020·5 cites·16 claims
- 2186US10361128B23D vertical FET with top and bottom gate contactsIBM·Filed 2017·Granted Jul 23, 2019·3 cites·15 claims
- 2285US7397641B2Apparatus and method for improved triggering and oscillation suppression of ESD clamping devicesIBM·Filed 2006·Granted Jul 8, 2008·11 cites·6 claims
- 2384US8856715B1Capacitor designs for integrated circuits utilizing self-aligned double patterning (SADP)GLOBALFOUNDRIES INC·Filed 2013·Granted Oct 7, 2014·8 cites·20 claims
- 2483US10529625B23D vertical FET with top and bottom gate contactsIBM·Filed 2018·Granted Jan 7, 2020·2 cites·20 claims
- 2583US8643987B2Current leakage in RC ESD clampsCHU ALBERT M·Filed 2012·Granted Feb 4, 2014·6 cites·18 claims
- 2683US7466171B2Voltage detection circuit and circuit for generating a trigger flag signalIBM·Filed 2007·Granted Dec 16, 2008·10 cites·20 claims
- 2783US6421784B1Programmable delay circuit having a fine delay element selectively receives input signal and output signal of coarse delay elementIBM·Filed 1999·Granted Jul 16, 2002·53 cites·27 claims
- 2881US6760881B2Method for combining refresh operation with parity validation in a DRAM-based content addressable memory (CAM)IBM·Filed 2001·Granted Jul 6, 2004·30 cites·20 claims
- 2978US10832971B2Fabricating tapered semiconductor devicesIBM·Filed 2018·Granted Nov 10, 2020·2 cites·20 claims
- 3077US11031296B23D vertical FET with top and bottom gate contactsIBM·Filed 2019·Granted Jun 8, 2021·1 cites·20 claims
- 3177US6487101B1Use of search lines as global bitlines in a cam designIBM·Filed 2001·Granted Nov 26, 2002·24 cites·18 claims
- 3276US8934312B2Process variation skew in an SRAM column architectureIBM·Filed 2013·Granted Jan 13, 2015·5 cites·20 claims
- 3374US10693005B2Reliable gate contacts over active areasIBM·Filed 2019·Granted Jun 23, 2020·1 cites·7 claims
- 3474US7573300B2Current control mechanism for dynamic logic keeper circuits in an integrated circuit and method of regulating sameIBM·Filed 2007·Granted Aug 11, 2009·7 cites·2 claims
- 3573US10614877B14T static random access memory bitcell retentionIBM·Filed 2019·Granted Apr 7, 2020·3 cites·20 claims
- 3673US10381480B2Reliable gate contacts over active areasINT BUSNIESS MACHINES CORPORATION·Filed 2017·Granted Aug 13, 2019·2 cites·9 claims
- 3772US8839054B2Read only memory (ROM) with redundancyBRACERAS GEORGE M·Filed 2012·Granted Sep 16, 2014·4 cites·13 claims
- 3872US6285229B1Digital delay line with low insertion delayIBM·Filed 1999·Granted Sep 4, 2001·30 cites·12 claims
- 3971US10424574B2Standard cell architecture with at least one gate contact over an active areaIBM·Filed 2017·Granted Sep 24, 2019·1 cites·13 claims
- 4071US9460811B2Read only memory (ROM) with redundancyIBM·Filed 2014·Granted Oct 4, 2016·2 cites·8 claims
- 4169US12506080B2Reduced capacitance between power via bar and gatesIBM·Filed 2022·Granted Dec 23, 2025·0 cites·24 claims
- 4269US12500144B2Backside self aligned skip viaIBM·Filed 2023·Granted Dec 16, 2025·0 cites·20 claims
- 4369US12417979B2Pass-through wiring in notched interconnectIBM·Filed 2023·Granted Sep 16, 2025·0 cites·20 claims
- 4469US2025301785A1Cross-couple connect in stacked field effect transistor semiconductorsIBM·Filed 2024·Application pending·0 cites
- 4568US12400960B2Vertical-transport field-effect transistor with backside gate contactIBM·Filed 2022·Granted Aug 26, 2025·0 cites·20 claims
- 4668US12342578B2Stacked layer memory suitable for SRAM and having a long cellIBM·Filed 2022·Granted Jun 24, 2025·0 cites·20 claims
- 4767US7471114B2Design structure for a current control mechanism for power networks and dynamic logic keeper circuitsIBM·Filed 2007·Granted Dec 30, 2008·5 cites·17 claims
- 4866US12295133B2SRAM with backside cross-coupleIBM·Filed 2022·Granted May 6, 2025·0 cites·20 claims
- 4966US12278184B2Vertically-stacked field effect transistor cellIBM·Filed 2022·Granted Apr 15, 2025·0 cites·18 claims
- 5066US7873921B2Structure for a voltage detection circuit in an integrated circuit and method of generating a trigger flag signalIBM·Filed 2007·Granted Jan 18, 2011·3 cites·5 claims
Showing the top 50 of 223 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →