Inventor · disambiguated record
Aldo Giovanni Cometti
Also filed as: COMETTI ALDO G · COMETTI ALDO GIOVANNI
21 granted patents·1 pending application·322 citations·filing 1996–2021
95Inventor score
Files withWESTERN DIGITAL TECH INC12STEC INC3COMETTI ALDO G2HGST Netherlands BV1HGST TECHNOLOGIES SANTA ANA INC1
Top patents by PatentIndex Score
22 records- 0198US9761308B1Systems and methods for adaptive read level adjustmentHGST Netherlands BV·Filed 2016·Granted Sep 12, 2017·65 cites·20 claims
- 0296US10236070B2Read level tracking and optimizationWESTERN DIGITAL TECH INC·Filed 2017·Granted Mar 19, 2019·14 cites·25 claims
- 0396US9047955B2Adjusting operating parameters for memory cells based on wordline address and cycle informationSTEC INC·Filed 2013·Granted Jun 2, 2015·26 cites·20 claims
- 0496US9007854B1Method and system for optimized soft decoding in a data storage deviceWESTERN DIGITAL TECH INC·Filed 2013·Granted Apr 14, 2015·36 cites·22 claims
- 0596US8737136B2Apparatus and method for determining a read level of a memory cell based on cycle informationCOMETTI ALDO G·Filed 2011·Granted May 27, 2014·60 cites·35 claims
- 0696US8644099B2Apparatus and method for determining a read level of a flash memory after an inactive period of timeCOMETTI ALDO G·Filed 2011·Granted Feb 4, 2014·42 cites·23 claims
- 0793US9270296B1Method and system for soft decoding through single readWESTERN DIGITAL TECH INC·Filed 2013·Granted Feb 23, 2016·20 cites·22 claims
- 0893US9195586B2Determining bias information for offsetting operating variations in memory cells based on wordline addressSTEC INC·Filed 2013·Granted Nov 24, 2015·15 cites·19 claims
- 0990US11101006B2Read level tracking and optimizationWESTERN DIGITAL TECH INC·Filed 2020·Granted Aug 24, 2021·2 cites·20 claims
- 1089US9224456B2Setting operating parameters for memory cells based on wordline address and cycle informationSTEC INC·Filed 2015·Granted Dec 29, 2015·9 cites·20 claims
- 1187US10748628B2Read level tracking and optimizationWESTERN DIGITAL TECHNOLOGIES INC·Filed 2019·Granted Aug 18, 2020·3 cites·20 claims
- 1285US10373695B2Methods and apparatus for read disturb detection and handlingWESTERN DIGITAL TECH INC·Filed 2016·Granted Aug 6, 2019·4 cites·23 claims
- 1383US10282111B2Adaptive wear levellingWESTERN DIGITAL TECH INC·Filed 2016·Granted May 7, 2019·4 cites·21 claims
- 1477US9377962B2Determining bias information for offsetting operating variations in memory cellsHGST TECHNOLOGIES SANTA ANA INC·Filed 2015·Granted Jun 28, 2016·4 cites·20 claims
- 1572US11621043B2Read level tracking and optimizationWESTERN DIGITAL TECH INC·Filed 2021·Granted Apr 4, 2023·0 cites·20 claims
- 1670US10496334B2Solid state drive using two-level indirection architectureWESTERN DIGITAL TECH INC·Filed 2018·Granted Dec 3, 2019·1 cites·21 claims
- 1769US10644727B2Code rate switching mechanism for flash memoryWESTERN DIGITAL TECH INC·Filed 2018·Granted May 5, 2020·1 cites·22 claims
- 1856US11190218B2Code rate switching mechanism for data storage systemWESTERN DIGITAL TECH INC·Filed 2020·Granted Nov 30, 2021·0 cites·20 claims
- 1956US10545810B2Method and apparatus for monitoring non-volatile memory read errors using background media scanWESTERN DIGITAL TECH INC·Filed 2016·Granted Jan 28, 2020·1 cites·17 claims
- 2051US5777498AData compensation/resynchronization circuit for phase lock loopsSGS THOMSON MICROELECTRONICS·Filed 1996·Granted Jul 7, 1998·14 cites·21 claims
- 2146US2015161001A1Misprogramming prevention in solid-state memoryWESTERN DIGITAL TECH INC·Filed 2013·Application pending·0 cites
- 2238USRE38045EData compensation/resynchronization circuit for phase lock loopsST MICROELECTRONICS INC·Filed 2000·Granted Mar 25, 2003·1 cites·41 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →