Inventor · disambiguated record
Alfred Griffin
Also filed as: GRIFFIN ALFRED · GRIFFIN ALFRED J · GRIFFIN ALFRED J JR · GRIFFIN JR ALFRED J
8 granted patents·8 pending applications·24 citations·filing 1998–2022
82Inventor score
Files withTEXAS INSTRUMENTS INC9AGGARWAL SANJEEV1GRIFFIN ALFRED J1GRIFFIN JR ALFRED J1MARTIN JAMES SCOTT1
Top patents by PatentIndex Score
16 records- 0166US7332425B2Simultaneous deposition and etch process for barrier layer formation in microelectronic device interconnectsTEXAS INSTRUMENTS INC·Filed 2005·Granted Feb 19, 2008·2 cites·18 claims
- 0261US7323409B2Method for forming a void free viaTEXAS INSTRUMENTS INC·Filed 2005·Granted Jan 29, 2008·3 cites·6 claims
- 0356US6617231B1Method for forming a metal extrusion free viaTEXAS INSTRUMENTS INC·Filed 2002·Granted Sep 9, 2003·8 cites·2 claims
- 0450US8236703B2Methods for removing contaminants from aluminum-comprising bond pads and integrated circuits therefromGRIFFIN JR ALFRED J·Filed 2008·Granted Aug 7, 2012·2 cites·19 claims
- 0547US2006009030A1Novel barrier integration scheme for high-reliability viasTEXAS INSTRUMENTS INC·Filed 2005·Application pending·0 cites
- 0647US2024142512A1Semiconductor device testingTEXAS INSTRUMENTS INC·Filed 2022·Application pending·0 cites
- 0746US6977437B2Method for forming a void free viaTEXAS INSTRUMENTS INC·Filed 2003·Granted Dec 20, 2005·3 cites·7 claims
- 0845US2011114597A1Barrier integration scheme for high-reliability viasTEXAS INSTRUMENTS INC·Filed 2010·Application pending·0 cites
- 0942US7998865B2Systems and methods for removing wafer edge residue and debris using a residue remover mechanismTEXAS INSTRUMENTS INC·Filed 2005·Granted Aug 16, 2011·0 cites·18 claims
- 1040US8110416B2AC impedance spectroscopy testing of electrical parametric structuresGRIFFIN ALFRED J·Filed 2008·Granted Feb 7, 2012·1 cites·18 claims
- 1139US2006266383A1Systems and methods for removing wafer edge residue and debris using a wafer clean solutionTEXAS INSTRUMENTS INC·Filed 2005·Application pending·0 cites
- 1239US2008207006A1Process for fabricating an integrated circuitMARTIN JAMES SCOTT·Filed 2007·Application pending·0 cites
- 1337US2006014378A1System and method to form improved seed layerAGGARWAL SANJEEV·Filed 2004·Application pending·0 cites
- 1434US6002259AElectrostatic adhesion tester for thin film conductorsRICE UNIVERSITY·Filed 1998·Granted Dec 14, 1999·5 cites·36 claims
- 1533US2003190801A1Method for forming a metal extrusion free viaFiled 2003·Application pending·0 cites
- 1624US2002013044A1HDP liner layer prior to HSQ/SOG deposition to reduce the amount of HSQ/SOG over the metal leadFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →