Inventor · disambiguated record
Alan B. Kyker
Also filed as: KYKER ALAN · KYKER ALAN B · KYKER ALAN BEECHER
42 granted patents·3 pending applications·1,268 citations·filing 1994–2021
98Inventor score
Top patents by PatentIndex Score
45 records- 0195US6535905B1Method and apparatus for thread switching within a multithreaded processorINTEL CORP·Filed 1999·Granted Mar 18, 2003·180 cites·81 claims
- 0294US6799268B1Branch ordering bufferINTEL CORP·Filed 2000·Granted Sep 28, 2004·138 cites·19 claims
- 0391US6981261B2Method and apparatus for thread switching within a multithreaded processorINTEL CORP·Filed 2002·Granted Dec 27, 2005·47 cites·81 claims
- 0490US6785890B2Method and system to perform a thread switching operation within a multithreaded processor based on detection of the absence of a flow of instruction information for a threadINTEL CORP·Filed 2002·Granted Aug 31, 2004·39 cites·16 claims
- 0589US6795845B2Method and system to perform a thread switching operation within a multithreaded processor based on detection of a branch instructionINTEL CORP·Filed 2002·Granted Sep 21, 2004·37 cites·18 claims
- 0689US6374350B1System and method of maintaining and utilizing multiple return stack buffersINTEL CORP·Filed 2000·Granted Apr 16, 2002·58 cites·16 claims
- 0787US6651158B2Determination of approaching instruction starvation of threads based on a plurality of conditionsINTEL CORP·Filed 2001·Granted Nov 18, 2003·39 cites·30 claims
- 0886US6715064B1Method and apparatus for performing sequential executions of elements in cooperation with a transformINTEL CORP·Filed 2000·Granted Mar 30, 2004·48 cites·23 claims
- 0984US6041403AMethod and apparatus for generating a microinstruction responsive to the specification of an operand, in addition to a microinstruction based on the opcode, of a macroinstructionINTEL CORP·Filed 1996·Granted Mar 21, 2000·115 cites·34 claims
- 1082US9753526B2Systems and methods for synergistic software-hardware power budget managementINTEL CORP·Filed 2014·Granted Sep 5, 2017·5 cites·22 claims
- 1181US11061463B2Systems and methods for synergistic software-hardware power budget managementINTEL CORP·Filed 2017·Granted Jul 13, 2021·2 cites·20 claims
- 1281US6151671ASystem and method of maintaining and utilizing multiple return stack buffersINTEL CORP·Filed 1998·Granted Nov 21, 2000·97 cites·6 claims
- 1380US6971104B2Method and system to perform a thread switching operation within a multithreaded processor based on dispatch of a quantity of instruction information for a full instructionINTEL CORP·Filed 2002·Granted Nov 29, 2005·18 cites·12 claims
- 1479US6854118B2Method and system to perform a thread switching operation within a multithreaded processor based on detection of a flow marker within an instruction informationINTEL CORP·Filed 2002·Granted Feb 8, 2005·16 cites·18 claims
- 1578US6308279B1Method and apparatus for power mode transition in a multi-thread processorINTEL CORP·Filed 1998·Granted Oct 23, 2001·61 cites·23 claims
- 1675US10025343B2Data transfer between asynchronous clock domainsRIFANI MICHAEL C·Filed 2011·Granted Jul 17, 2018·5 cites·21 claims
- 1775US6865740B2Method and system to insert a flow marker into an instruction stream to indicate a thread switching operation within a multithreaded processorINTEL CORP·Filed 2002·Granted Mar 8, 2005·12 cites·16 claims
- 1875US6055630ASystem and method for processing a plurality of branch instructions by a plurality of storage devices and pipeline unitsINTEL CORP·Filed 1998·Granted Apr 25, 2000·73 cites·23 claims
- 1974US6850961B2Method and system to perform a thread switching operation within a multithreaded processor based on detection of a stall conditionINTEL CORP·Filed 2002·Granted Feb 1, 2005·11 cites·20 claims
- 2071US7010669B2Determining whether thread fetch operation will be blocked due to processing of another threadINTEL CORP·Filed 2003·Granted Mar 7, 2006·13 cites·9 claims
- 2170US11650652B2Systems and methods for synergistic software-hardware power budget managementINTEL CORP·Filed 2021·Granted May 16, 2023·0 cites·20 claims
- 2266US6564298B2Front end system having multiple decoding modesINTEL CORP·Filed 2000·Granted May 13, 2003·9 cites·27 claims
- 2365US7114057B2System and method for storing immediate dataINTEL CORP·Filed 2001·Granted Sep 26, 2006·7 cites·23 claims
- 2464US6594734B1Method and apparatus for self modifying code detection using a translation lookaside bufferINTEL CORP·Filed 1999·Granted Jul 15, 2003·45 cites·21 claims
- 2563US6711669B2System and method for storing immediate dataINTEL CORP·Filed 2003·Granted Mar 23, 2004·6 cites·8 claims
- 2663US6338132B1System and method for storing immediate dataINTEL CORP·Filed 1998·Granted Jan 8, 2002·28 cites·8 claims
- 2762US7730281B2System and method for storing immediate dataINTEL CORP·Filed 2007·Granted Jun 1, 2010·1 cites·20 claims
- 2862US6578138B1System and method for unrolling loops in a trace cacheINTEL CORP·Filed 1999·Granted Jun 10, 2003·38 cites·22 claims
- 2961US7080236B2Updating stack pointer based on instruction bit indicator without executing an update microinstructionINTEL CORP·Filed 2002·Granted Jul 18, 2006·7 cites·33 claims
- 3061US6775786B2Method and apparatus for power mode transition in a multi-thread processorINTEL CORP·Filed 2001·Granted Aug 10, 2004·8 cites·46 claims
- 3161US5537560AMethod and apparatus for conditionally generating a microinstruction that selects one of two values based upon control states of a microprocessorINTEL CORP·Filed 1994·Granted Jul 16, 1996·35 cites·21 claims
- 3259US7334115B1Detection, recovery and prevention of bogus branchesINTEL CORP·Filed 2000·Granted Feb 19, 2008·8 cites·25 claims
- 3356US10599178B2Data transfer between asynchronous clock domainsINTEL CORP·Filed 2018·Granted Mar 24, 2020·0 cites·17 claims
- 3452US6625717B2Single cycle linear address calculation for relative branch addressingINTEL CORP·Filed 2002·Granted Sep 23, 2003·2 cites·26 claims
- 3550US6981163B2Method and apparatus for power mode transition in a multi-thread processorINTEL CORP·Filed 2004·Granted Dec 27, 2005·2 cites·25 claims
- 3650US6591344B2Method and system for an INUSE field resource management schemeINTEL CORP·Filed 2002·Granted Jul 8, 2003·1 cites·34 claims
- 3749US6026477ABranch recovery mechanism to reduce processor front end stall time by providing path information for both correct and incorrect instructions mixed in the instruction poolINTEL CORP·Filed 1997·Granted Feb 15, 2000·21 cites·17 claims
- 3847US7321963B2System and method for storing immediate dataINTEL CORP·Filed 2004·Granted Jan 22, 2008·0 cites·15 claims
- 3946US6721849B2Front end system having multiple decoding modesINTEL CORP·Filed 2003·Granted Apr 13, 2004·0 cites·39 claims
- 4046US6467027B1Method and system for an INUSE field resource management schemeINTEL CORP·Filed 1999·Granted Oct 15, 2002·15 cites·22 claims
- 4145US6493821B1Recovery from writeback stage event signal or micro-branch misprediction using instruction sequence number indexed state information tableINTEL CORP·Filed 1998·Granted Dec 10, 2002·17 cites·33 claims
- 4244US2004088525A1Method and apparatus for performing sequential executions of elements in cooperation with a transformFiled 2003·Application pending·0 cites
- 4340US2002083307A1System and method for partial merges for sub-register data operationsFiled 2000·Application pending·0 cites
- 4440US2004015675A1SMC detection and reverse translation in a translation lookaside bufferFiled 2003·Application pending·0 cites
- 4533US6502177B1Single cycle linear address calculation for relative branch addressingINTEL CORP·Filed 1999·Granted Dec 31, 2002·4 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →