Inventor · disambiguated record
Ali Lehaf
Also filed as: LEHAF ALI
7 granted patents·13 pending applications·17 citations·filing 2018–2024
79Inventor score
Top patents by PatentIndex Score
20 records- 0194US10431537B1Electromigration resistant and profile consistent contact arraysINTEL CORP·Filed 2018·Granted Oct 1, 2019·11 cites·26 claims
- 0290US11309239B2Electromigration resistant and profile consistent contact arraysINTEL CORP·Filed 2020·Granted Apr 19, 2022·2 cites·20 claims
- 0389US11935857B2Surface finishes with low RBTV for fine and mixed bump pitch architecturesINTEL CORP·Filed 2022·Granted Mar 19, 2024·1 cites·22 claims
- 0481US11488918B2Surface finishes with low rBTV for fine and mixed bump pitch architecturesINTEL CORP·Filed 2018·Granted Nov 1, 2022·3 cites·15 claims
- 0576US11699648B2Electromigration resistant and profile consistent contact arraysTAHOE RES LTD·Filed 2022·Granted Jul 11, 2023·0 cites·20 claims
- 0670US2024243088A1Copperless regions to control plating growthINTEL CORP·Filed 2024·Application pending·0 cites
- 0762US10854541B2Electromigration resistant and profile consistent contact arraysINTEL CORP·Filed 2019·Granted Dec 1, 2020·0 cites·24 claims
- 0856US2025201720A1Methods, systems, apparatus, and articles of manufacture to reduce intermetallic compound formation in integrated circuit packagesINTEL CORP·Filed 2023·Application pending·0 cites
- 0955US2025112164A1Controlling substrate bump heightINTEL CORP·Filed 2023·Application pending·0 cites
- 1054US2024213198A1Under bump metallizations, solder compositions, and structures for die interconnects on integrated circuit packagingINTEL CORP·Filed 2022·Application pending·0 cites
- 1153US12334422B2Methods and apparatus to reduce defects in interconnects between semicondcutor dies and package substratesINTEL CORP·Filed 2021·Granted Jun 17, 2025·0 cites·24 claims
- 1253US2025218911A1Electrolytic cobalt-iron-palladium-gold as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 1353US2025219002A1Electrolytic indium-palladium-gold as a surface finish for embedded die attachmentsINTEL CORP·Filed 2023·Application pending·0 cites
- 1451US2021082852A1Copperless regions to control plating growthINTEL CORP·Filed 2019·Application pending·0 cites
- 1551US2024096809A1Microelectronic assemblies with mixed copper and solder interconnects having different thicknessesINTEL CORP·Filed 2022·Application pending·0 cites
- 1650US2024105575A1Electrolytic surface finish architectureINTEL CORP·Filed 2022·Application pending·0 cites
- 1749US2024006298A1Substrate having one or more electrical interconnectsINTEL CORP·Filed 2022·Application pending·0 cites
- 1848US2023091379A1First level interconnect under bump metallizations for fine pitch heterogeneous applicationsINTEL CORP·Filed 2021·Application pending·0 cites
- 1947US2023420346A1Single lithography methods for interconnect architecturesINTEL CORP·Filed 2022·Application pending·0 cites
- 2044US2024079530A1Ic package with micro ledsINTEL CORP·Filed 2022·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →