Inventor · disambiguated record
Alon Naveh
Also filed as: NAVEH ALON
100 granted patents·14 pending applications·922 citations·filing 2001–2024
99Inventor score
Top patents by PatentIndex Score
114 records- 0194US12228988B2Merging of power events related to estimated power consumption of different devices in a hierarchical power management system in an integrated circuit (IC) chip to perform power throttlingQUALCOMM INC·Filed 2023·Granted Feb 18, 2025·6 cites·44 claims
- 0294US11687139B2Multi-level CPU high current protectionINTEL CORP·Filed 2022·Granted Jun 27, 2023·2 cites·20 claims
- 0394US7502948B2Method, system, and apparatus for selecting a maximum operation point based on number of active cores and performance level of each of the active coresINTEL CORP·Filed 2004·Granted Mar 10, 2009·66 cites·18 claims
- 0494US7451333B2Coordinating idle state transitions in multi-core processorsINTEL CORP·Filed 2004·Granted Nov 11, 2008·94 cites·29 claims
- 0592US9158693B2Dynamically controlling cache size to maximize energy efficiencyANANTHAKRISHNAN AVINASH N·Filed 2011·Granted Oct 13, 2015·14 cites·11 claims
- 0692US7966511B2Power management coordination in multi-core processorsINTEL CORP·Filed 2004·Granted Jun 21, 2011·73 cites·38 claims
- 0792US7962771B2Method, system, and apparatus for rerouting interrupts in a multi-core processorINTEL CORP·Filed 2007·Granted Jun 14, 2011·28 cites·28 claims
- 0891US11733757B2Hierarchical power management architecture for SoC-based electronic devicesNUVIA INC·Filed 2022·Granted Aug 22, 2023·2 cites·19 claims
- 0991US10509576B2Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devicesINTEL CORP·Filed 2017·Granted Dec 17, 2019·5 cites·20 claims
- 1091US10067553B2Dynamically controlling cache size to maximize energy efficiencyINTEL CORP·Filed 2016·Granted Sep 4, 2018·5 cites·13 claims
- 1191US7523327B2System and method of coherent data transfer during processor idle statesINTEL CORP·Filed 2005·Granted Apr 21, 2009·19 cites·19 claims
- 1291US7191349B2Mechanism for processor power state aware distribution of lowest priority interruptINTEL CORP·Filed 2002·Granted Mar 13, 2007·59 cites·36 claims
- 1390US9471490B2Dynamically controlling cache size to maximize energy efficiencyINTEL CORP·Filed 2015·Granted Oct 18, 2016·5 cites·20 claims
- 1490US9400545B2Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devicesSODHI INDER M·Filed 2011·Granted Jul 26, 2016·11 cites·24 claims
- 1590US8650424B2Method and apparatus to control power consumption of a plurality of processor coresROTEM EFRAIM·Filed 2009·Granted Feb 11, 2014·14 cites·20 claims
- 1690US7137018B2Active state link power managementINTEL CORP·Filed 2002·Granted Nov 14, 2006·47 cites·39 claims
- 1789US9075614B2Managing power consumption in a multi-core processorINTEL CORP·Filed 2013·Granted Jul 7, 2015·12 cites·11 claims
- 1888US9720730B2Providing an asymmetric multicore processor system transparently to an operating systemGINZBURG BORIS·Filed 2011·Granted Aug 1, 2017·15 cites·20 claims
- 1988US8726048B2Power management coordination in multi-core processorsNAVEH ALON·Filed 2011·Granted May 13, 2014·8 cites·33 claims
- 2088US7584375B2Active state link power managementINTEL CORP·Filed 2006·Granted Sep 1, 2009·15 cites·21 claims
- 2187US8799687B2Method, apparatus, and system for energy efficiency and energy conservation including optimizing C-state selection under variable wakeup ratesNAVEH ALON·Filed 2011·Granted Aug 5, 2014·9 cites·20 claims
- 2287US7932639B2Simultaneous multi-voltage rail voltage regulation messagesINTEL CORP·Filed 2007·Granted Apr 26, 2011·25 cites·13 claims
- 2386US10372197B2User level control of power management policiesINTEL CORP·Filed 2016·Granted Aug 6, 2019·3 cites·20 claims
- 2486US9619009B2Operating point management in multi-core architecturesROTEM EFRAIM·Filed 2010·Granted Apr 11, 2017·6 cites·31 claims
- 2586US9074947B2Estimating temperature of a processor core in a low power state without thermal sensor informationANANTHAKRISHNAN AVINASH N·Filed 2011·Granted Jul 7, 2015·8 cites·16 claims
- 2686US9069555B2Managing power consumption in a multi-core processorFETZER ERIC·Filed 2012·Granted Jun 30, 2015·17 cites·11 claims
- 2785US10379596B2Providing an interface for demotion control information in a processorINTEL CORP·Filed 2016·Granted Aug 13, 2019·5 cites·18 claims
- 2885US9092210B2Controlling current transients in a processorROTEM EFRAIM·Filed 2011·Granted Jul 28, 2015·9 cites·17 claims
- 2985US7013406B2Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic deviceINTEL CORP·Filed 2002·Granted Mar 14, 2006·39 cites·21 claims
- 3084US7363523B2Method and apparatus for controlling power management state transitionsINTEL CORP·Filed 2004·Granted Apr 22, 2008·41 cites·29 claims
- 3183US9268378B2Techniques and system for managing platform temperatureINTEL CORP·Filed 2013·Granted Feb 23, 2016·7 cites·27 claims
- 3283US8707062B2Method and apparatus for powered off processor core modeJAHAGIRDAR SANJEEV·Filed 2010·Granted Apr 22, 2014·4 cites·20 claims
- 3383US7725745B2Power aware software pipelining for hardware acceleratorsINTEL CORP·Filed 2006·Granted May 25, 2010·12 cites·15 claims
- 3483US7225350B2Active state link power managementINTEL CORP·Filed 2006·Granted May 29, 2007·9 cites·14 claims
- 3583US7076672B2Method and apparatus for performance effective power throttlingINTEL CORP·Filed 2002·Granted Jul 11, 2006·35 cites·38 claims
- 3682US9792064B2Method, apparatus, and system for energy efficiency and energy conservation including autonomous hardware-based deep power down in devicesINTEL CORP·Filed 2016·Granted Oct 17, 2017·2 cites·19 claims
- 3781US10185566B2Migrating tasks between asymmetric computing elements of a multi-core processorNAVEH ALON·Filed 2012·Granted Jan 22, 2019·5 cites·19 claims
- 3881US10162687B2Selective migration of workloads between heterogeneous compute elements based on evaluation of migration performance benefit and available energy and thermal budgetsINTEL CORP·Filed 2012·Granted Dec 25, 2018·5 cites·25 claims
- 3981US9329900B2Hetergeneous processor apparatus and methodINTEL CORP·Filed 2012·Granted May 3, 2016·6 cites·25 claims
- 4080US9098261B2User level control of power management policiesSISTLA KRISHNAKANTH V·Filed 2011·Granted Aug 4, 2015·4 cites·16 claims
- 4180US8819461B2Method, apparatus, and system for energy efficiency and energy conservation including improved processor core deep power down exit latency by using register secondary uninterrupted power supplySODHI INDER M·Filed 2011·Granted Aug 26, 2014·4 cites·20 claims
- 4280US7908496B2Systems and methods for communicating voltage regulation information between a voltage regulator and an integrated circuitINTEL CORP·Filed 2007·Granted Mar 15, 2011·10 cites·24 claims
- 4379US11287871B2Operating point management in multi-core architecturesINTEL CORP·Filed 2018·Granted Mar 29, 2022·1 cites·31 claims
- 4479US7237128B2Method and apparatus to dynamically change an operating frequency and operating voltage of an electronic deviceINTEL CORP·Filed 2004·Granted Jun 26, 2007·23 cites·28 claims
- 4578US9477627B2Interconnect to communicate information uni-directionallyINTEL CORP·Filed 2012·Granted Oct 25, 2016·3 cites·19 claims
- 4678US9170624B2User level control of power management policiesINTEL CORP·Filed 2013·Granted Oct 27, 2015·3 cites·18 claims
- 4777US9841807B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2015·Granted Dec 12, 2017·1 cites·24 claims
- 4877US7761720B2Mechanism for processor power state aware distribution of lowest priority interruptsINTEL CORP·Filed 2007·Granted Jul 20, 2010·7 cites·22 claims
- 4976US9141180B2Method and apparatus for a zero voltage processor sleep stateINTEL CORP·Filed 2015·Granted Sep 22, 2015·1 cites·6 claims
- 5076US9081687B2Method and apparatus for MONITOR and MWAIT in a distributed cache architectureOFFEN ZEEV·Filed 2007·Granted Jul 14, 2015·8 cites·17 claims
Showing the top 50 of 114 patent records by PatentIndex Score.
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →