Inventor · disambiguated record
Alberto Ros
Also filed as: ROS ALBERTO
11 granted patents·22 citations·filing 2013–2020
84Inventor score
Technology areasG06F
Top patents by PatentIndex Score
11 records- 0186US9274960B2System and method for simplifying cache coherence using multiple write policiesKAXIRAS STEFANOS·Filed 2013·Granted Mar 1, 2016·14 cites·27 claims
- 0281US11119920B2Systems and methods for non-speculative store coalescing and generating atomic write sets using address subsetsETA SCALE AB·Filed 2019·Granted Sep 14, 2021·3 cites·16 claims
- 0378US11068410B2Multi-core computer systems with private/shared cache line indicatorsETA SCALE AB·Filed 2019·Granted Jul 20, 2021·2 cites·11 claims
- 0476US11334485B2System and method for dynamic enforcement of store atomicityETA SCALE AB·Filed 2019·Granted May 17, 2022·2 cites·20 claims
- 0573US11188464B2System and method for self-invalidation, self-downgrade cachecoherence protocolsETA SCALE AB·Filed 2019·Granted Nov 30, 2021·1 cites·20 claims
- 0660US11237966B2System and method for event monitoring in cache coherence protocols without explicit invalidationsETA SCALE AB·Filed 2019·Granted Feb 1, 2022·0 cites·35 claims
- 0754US10528471B2System and method for self-invalidation, self-downgrade cachecoherence protocolsETA SCALE AB·Filed 2017·Granted Jan 7, 2020·0 cites·16 claims
- 0849US11106468B2System and method for non-speculative reordering of load accessesETA SCALE AB·Filed 2018·Granted Aug 31, 2021·0 cites·14 claims
- 0947US10324861B2Systems and methods for coherence in clustered cache hierarchiesROS ALBERTO·Filed 2016·Granted Jun 18, 2019·0 cites·7 claims
- 1045US10387312B2System and method for event monitoring in cache coherence protocols without explicit invalidationsKAXIRAS STEFANOS·Filed 2015·Granted Aug 20, 2019·0 cites·14 claims
- 1141US11163576B2Systems and methods for invisible speculative executionETA SCALE AB·Filed 2020·Granted Nov 2, 2021·0 cites·16 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →