Inventor · disambiguated record
Alex See
Also filed as: SEE ALEX · SEE ALEX KAI HUNG
14 granted patents·1 pending application·406 citations·filing 2000–2016
94Inventor score
Files withCHARTERED SEMICONDUCTOR MFG9GLOBALFOUNDRIES SG PTE LTD2LIM YEOW KHENG2CHARTERED SEMICONDUCTOR MANFAC1CHARTERED SEMICONDUCTORS MAUFA1
Top patents by PatentIndex Score
15 records- 0193US6406975B1Method for fabricating an air gap shallow trench isolation (STI) structureCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Jun 18, 2002·84 cites·18 claims
- 0293US6380106B1Method for fabricating an air gap metallization scheme that reduces inter-metal capacitance of interconnect structuresCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 30, 2002·84 cites·11 claims
- 0389US6380084B1Method to form high performance copper damascene interconnects by de-coupling via and metal line fillingCHARTERED SEMICONDUCTOR MFG·Filed 2000·Granted Apr 30, 2002·59 cites·33 claims
- 0487US7585768B2Combined copper plating method to improve gap fillCHARTERED SEMICONDUCTOR MFG·Filed 2006·Granted Sep 8, 2009·14 cites·12 claims
- 0587US7094669B2Structure and method of liner air gap formationCHARTERED SEMICONDUCTOR MFG·Filed 2004·Granted Aug 22, 2006·46 cites·29 claims
- 0683US6558994B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTORS MAUFA·Filed 2001·Granted May 6, 2003·36 cites·13 claims
- 0783US6410429B1Method for fabricating void-free epitaxial-CoSi2 with ultra-shallow junctionsCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Jun 25, 2002·33 cites·15 claims
- 0876US7989338B2Grain boundary blocking for stress migration and electromigration improvement in CU interconnectsGLOBALFOUNDRIES SG PTE LTD·Filed 2005·Granted Aug 2, 2011·8 cites·22 claims
- 0968US6613649B2Method for buffer STI scheme with a hard mask layer as an oxidation barrierCHARTERED SEMICONDUCTOR MFG·Filed 2001·Granted Sep 2, 2003·16 cites·21 claims
- 1060US7119010B2Integrated circuit with self-aligned line and via and manufacturing method thereforCHARTERED SEMICONDUCTOR MANFAC·Filed 2002·Granted Oct 10, 2006·10 cites·9 claims
- 1158US6518133B1Method for fabricating a small dimensional gate with elevated source/drain structuresCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 11, 2003·8 cites·21 claims
- 1257US6849928B2Dual silicon-on-insulator device wafer dieCHARTERED SEMICONDUCTOR MFG·Filed 2002·Granted Feb 1, 2005·6 cites·10 claims
- 1356US8766454B2Integrated circuit with self-aligned line and viaLIM YEOW KHENG·Filed 2006·Granted Jul 1, 2014·1 cites·10 claims
- 1448US2016233157A1Slot designs in wide metal linesGLOBALFOUNDRIES SG PTE LTD·Filed 2016·Application pending·0 cites
- 1544US9318378B2Slot designs in wide metal linesLIM YEOW KHENG·Filed 2004·Granted Apr 19, 2016·1 cites·18 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →