Inventor · disambiguated record
Alexander J. Suess
Also filed as: SUESS ALEXANDER · SUESS ALEXANDER J · SUESS ALEXANDER JOEL
37 granted patents·6 pending applications·243 citations·filing 1999–2023
97Inventor score
Top patents by PatentIndex Score
43 records- 0193US9483604B1Variable accuracy parameter modeling in statistical timingIBM·Filed 2015·Granted Nov 1, 2016·9 cites·14 claims
- 0292US9501609B1Selection of corners and/or margins using statistical static timing analysis of an integrated circuitIBM·Filed 2015·Granted Nov 22, 2016·10 cites·15 claims
- 0391US7117466B2System and method for correlated process pessimism removal for static timing analysisIBM·Filed 2003·Granted Oct 3, 2006·75 cites·28 claims
- 0490US9418188B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 16, 2016·5 cites·1 claims
- 0588US10216875B2Leverage cycle stealing within optimization flowsIBM·Filed 2017·Granted Feb 26, 2019·4 cites·8 claims
- 0687US10013516B2Selection of corners and/or margins using statistical static timing analysis of an integrated circuitIBM·Filed 2016·Granted Jul 3, 2018·4 cites·18 claims
- 0787US9436791B1Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2015·Granted Sep 6, 2016·4 cites·20 claims
- 0886US10558775B2Memory element graph-based placement in integrated circuit designIBM·Filed 2017·Granted Feb 11, 2020·4 cites·17 claims
- 0984US7398491B2Method for fast incremental calculation of an impact of coupled noise on timingIBM·Filed 2006·Granted Jul 8, 2008·14 cites·18 claims
- 1083US9418201B1Integration of functional analysis and common path pessimism removal in static timing analysisIBM·Filed 2015·Granted Aug 16, 2016·3 cites·17 claims
- 1182US9747400B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Aug 29, 2017·2 cites·1 claims
- 1282US9703914B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Jul 11, 2017·2 cites·20 claims
- 1378US10540465B2Leverage cycle stealing within optimization flowsIBM·Filed 2019·Granted Jan 21, 2020·1 cites·1 claims
- 1478US9922149B2Integration of functional analysis and common path pessimism removal in static timing analysisIBM·Filed 2016·Granted Mar 20, 2018·2 cites·17 claims
- 1578US7937604B2Method for generating a skew schedule for a clock distribution network containing gating elementsIBM·Filed 2007·Granted May 3, 2011·10 cites·9 claims
- 1677US10902167B1Feedback-aware slack stealing across transparent latches empowering performance optimization of digital integrated circuitsIBM·Filed 2019·Granted Jan 26, 2021·2 cites·20 claims
- 1777US7694254B2Method, computer program product, and apparatus for static timing with run-time reductionIBM·Filed 2007·Granted Apr 6, 2010·8 cites·20 claims
- 1876US10552562B2Leverage cycle stealing within optimization flowsIBM·Filed 2017·Granted Feb 4, 2020·1 cites·12 claims
- 1975US6615395B1Method for handling coupling effects in static timing analysisIBM·Filed 1999·Granted Sep 2, 2003·72 cites·25 claims
- 2070US10706194B2Boundary assertion-based power recovery in integrated circuit designIBM·Filed 2018·Granted Jul 7, 2020·1 cites·14 claims
- 2170US9646122B2Variable accuracy parameter modeling in statistical timingIBM·Filed 2016·Granted May 9, 2017·1 cites·20 claims
- 2269US8302049B2Method for enabling multiple incompatible or costly timing environment for efficient timing closureMUSANTE FRANK J·Filed 2010·Granted Oct 30, 2012·4 cites·20 claims
- 2367US9785735B1Parallel incremental global routingIBM·Filed 2016·Granted Oct 10, 2017·1 cites·20 claims
- 2466US10970447B2Leverage cycle stealing within optimization flowsIBM·Filed 2019·Granted Apr 6, 2021·0 cites·13 claims
- 2566US9785737B2Parallel multi-threaded common path pessimism removal in multiple pathsIBM·Filed 2015·Granted Oct 10, 2017·1 cites·20 claims
- 2663US11080443B2Memory element graph-based placement in integrated circuit designIBM·Filed 2019·Granted Aug 3, 2021·0 cites·13 claims
- 2761US10606970B2Selection of corners and/or margins using statistical static timing analysis of an integrated circuitIBM·Filed 2018·Granted Mar 31, 2020·0 cites·20 claims
- 2861US2018239845A1Leverage cycle stealing within optimization flowsIBM·Filed 2017·Application pending·0 cites
- 2960US9075948B2Method of improving timing critical cells for physical design in the presence of local placement congestionIBM·Filed 2013·Granted Jul 7, 2015·1 cites·20 claims
- 3059US11916384B2Region-based power grid generation through modification of an initial power grid based on timing analysisIBM·Filed 2021·Granted Feb 27, 2024·0 cites·20 claims
- 3159US10210297B2Optimizing placement of circuit resources using a globally accessible placement memoryIBM·Filed 2016·Granted Feb 19, 2019·0 cites·1 claims
- 3257US2025191995A1Thermal transfer vias and semiconductor via structure for enhanced thermal transferIBM·Filed 2023·Application pending·0 cites
- 3356US7650246B2Process and apparatus for estimating circuit delayIBM·Filed 2005·Granted Jan 19, 2010·2 cites·30 claims
- 3451US2024330556A1Location aware timing analysis of a digital integrated circuitIBM·Filed 2023·Application pending·0 cites
- 3551US2025036850A1Method of predicting failure in a circuit design caused by noise impactIBM·Filed 2023·Application pending·0 cites
- 3650US11030367B2Out-of-context feedback hierarchical large block synthesis (HLBS) optimizationIBM·Filed 2019·Granted Jun 8, 2021·0 cites·20 claims
- 3750US10755017B2Cell placement in a circuit with shared inputs and outputsIBM·Filed 2018·Granted Aug 25, 2020·0 cites·21 claims
- 3849US11983477B2Routing layer re-optimization in physical synthesisIBM·Filed 2021·Granted May 14, 2024·0 cites·18 claims
- 3948US10776543B2Automated region based optimization of chip manufactureIBM·Filed 2018·Granted Sep 15, 2020·0 cites·18 claims
- 4047US9639654B2Managing virtual boundaries to enable lock-free concurrent region optimization of an integrated circuitIBM·Filed 2014·Granted May 2, 2017·0 cites·15 claims
- 4141US8495553B2Native threshold voltage switchingANTONY GEORGE·Filed 2011·Granted Jul 23, 2013·0 cites·20 claims
- 4241US2019362043A1Dynamic update of macro timing models during higher-level timing analysisIBM·Filed 2018·Application pending·0 cites
- 4339US2001046617A1Fuel cell system and method for operating a fuel cell systemFiled 2001·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →