Inventor · disambiguated record
Aman Gayasen
Also filed as: GAYASEN AMAN
12 granted patents·3 pending applications·42 citations·filing 2014–2023
86Inventor score
Files withXILINX INC15
Top patents by PatentIndex Score
15 records- 0193US10331836B1Loop optimization for implementing circuit designs in hardwareXILINX INC·Filed 2017·Granted Jun 25, 2019·20 cites·20 claims
- 0285US10303833B1Parallelizing timing-based operations for circuit designsXILINX INC·Filed 2017·Granted May 28, 2019·6 cites·20 claims
- 0384US8984462B1Physical optimization for timing closure for an integrated circuitXILINX INC·Filed 2014·Granted Mar 17, 2015·8 cites·20 claims
- 0480US10943042B1Data flow graph optimization techniques for RTL loops with conditional-exit statementsXILINX INC·Filed 2020·Granted Mar 9, 2021·2 cites·20 claims
- 0573US10839118B1Optimization-aware incremental synthesisXILINX INC·Filed 2018·Granted Nov 17, 2020·2 cites·17 claims
- 0672US10586005B1Incremental synthesis for changes to a circuit designXILINX INC·Filed 2018·Granted Mar 10, 2020·2 cites·20 claims
- 0766US10534885B1Modifying data flow graphs using range informationXILINX INC·Filed 2018·Granted Jan 14, 2020·1 cites·20 claims
- 0865US10789401B1Folding multiply-and-accumulate logicXILINX INC·Filed 2019·Granted Sep 29, 2020·1 cites·20 claims
- 0956US11586791B1Visualization of data buses in circuit designsXILINX INC·Filed 2021·Granted Feb 21, 2023·0 cites·20 claims
- 1054US2025200260A1Mitigation of control set packing restrictions for integrated circuitsXILINX INC·Filed 2023·Application pending·0 cites
- 1153US2025077760A1Control set optimization for circuit designs by detection of registers with redundant resetsXILINX INC·Filed 2023·Application pending·0 cites
- 1247US11829733B2Synthesis flow for data processing engine array applications relying on hardware library packagesXILINX INC·Filed 2021·Granted Nov 28, 2023·0 cites·19 claims
- 1347US2024193225A1Synthesis for matrix multiplication using a data processing arrayXILINX INC·Filed 2022·Application pending·0 cites
- 1444US11768663B1Compaction of multiplier and adder circuitsXILINX INC·Filed 2020·Granted Sep 26, 2023·0 cites·20 claims
- 1538US11755801B1Data flow graph refinement using range set information for improved synthesisXILINX INC·Filed 2020·Granted Sep 12, 2023·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →