Inventor · disambiguated record
Amar Guettaf
Also filed as: GUETTAF AMAR
16 granted patents·3 pending applications·125 citations·filing 2002–2012
92Inventor score
Top patents by PatentIndex Score
19 records- 0190US7058868B2Scan testing mode control of gated clock signals for memory devicesBROADCOM CORP·Filed 2003·Granted Jun 6, 2006·48 cites·8 claims
- 0276US7089471B2Scan testing mode control of gated clock signals for flip-flopsBROADCOM CORP·Filed 2003·Granted Aug 8, 2006·14 cites·6 claims
- 0374US7131045B2Systems and methods for scan test access using bond pad test access circuitsBROADCOM CORP·Filed 2003·Granted Oct 31, 2006·13 cites·7 claims
- 0467US7500165B2Systems and methods for controlling clock signals during scan testing integrated circuitsBROADCOM CORP·Filed 2004·Granted Mar 3, 2009·12 cites·14 claims
- 0565US8856559B2Integrated circuit allowing to test a power management unit based on or more conditions and configuring the plurality of pins to operate in normal and test modeALARCON VERONICA·Filed 2012·Granted Oct 7, 2014·1 cites·20 claims
- 0663US7441164B2Memory bypass with support for path delay testBROADCOM CORP·Filed 2002·Granted Oct 21, 2008·13 cites·12 claims
- 0763US7032202B2System and method for implementing a flexible top level scan architecture using a partitioning algorithm to balance the scan chainsBROADCOM CORP·Filed 2002·Granted Apr 18, 2006·10 cites·40 claims
- 0858US8074132B2Protecting data on integrated circuitGUETTAF AMAR·Filed 2008·Granted Dec 6, 2011·4 cites·22 claims
- 0954US6968519B2System and method for using IDDQ pattern generation for burn-in testsBROADCOM CORP·Filed 2002·Granted Nov 22, 2005·4 cites·16 claims
- 1045US7424417B2System and method for clock domain grouping using data path relationshipsBROADCOM CORP·Filed 2002·Granted Sep 9, 2008·3 cites·19 claims
- 1141US6822439B2Control of tristate buses during scan testBROADCOM CORP·Filed 2003·Granted Nov 23, 2004·2 cites·22 claims
- 1240US7062693B2Methodology for selectively testing portions of an integrated circuitBROADCOM CORP·Filed 2003·Granted Jun 13, 2006·1 cites·19 claims
- 1337US7581150B2Methods and computer program products for debugging clock-related scan testing failures of integrated circuitsBROADCOM CORP·Filed 2004·Granted Aug 25, 2009·0 cites·12 claims
- 1436US7395468B2Methods for debugging scan testing failures of integrated circuitsBROADCOM CORP·Filed 2004·Granted Jul 1, 2008·0 cites·26 claims
- 1535US7558722B2Debug method for mismatches occurring during the simulation of scan patternsBROADCOM CORP·Filed 2002·Granted Jul 7, 2009·0 cites·13 claims
- 1633US2008282110A1Scan clock architecture supporting slow speed scan, at speed scan, and logic bistGUETTAF AMAR·Filed 2007·Application pending·0 cites
- 1733US2008282122A1Single scan clock in a multi-clock domainGUETTAF AMAR·Filed 2007·Application pending·0 cites
- 1832US2008082879A1JTAG boundary scan compliant testing architecture with full and partial disableGUETTAF AMAR·Filed 2006·Application pending·0 cites
- 1930US8310263B2Control of tristate buses during scan testKODIHALLI HIMAKIRAN·Filed 2004·Granted Nov 13, 2012·0 cites·6 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →