Inventor · disambiguated record
Anthony Gus Aipperspach
Also filed as: AIPPERSPACH ANTHONY G · AIPPERSPACH ANTHONY GUS
62 granted patents·12 pending applications·1,101 citations·filing 1984–2019
99Inventor score
Top patents by PatentIndex Score
74 records- 0195US6181614B1Dynamic repair of redundant memory arrayIBM·Filed 1999·Granted Jan 30, 2001·137 cites·22 claims
- 0293US6538522B1Method and ring oscillator for evaluating dynamic circuitsIBM·Filed 2001·Granted Mar 25, 2003·53 cites·20 claims
- 0391US5778243AMulti-threaded cell for a memoryIBM·Filed 1996·Granted Jul 7, 1998·211 cites·35 claims
- 0489US6657886B1Split local and continuous bitline for fast domino read SRAMIBM·Filed 2002·Granted Dec 2, 2003·52 cites·11 claims
- 0584US6643804B1Stability test for silicon on insulator SRAM memory cells utilizing bitline precharge stress operations to stress memory cells under testIBM·Filed 2000·Granted Nov 4, 2003·37 cites·31 claims
- 0682US7528646B2Electrically programmable fuse sense circuitIBM·Filed 2006·Granted May 5, 2009·14 cites·1 claims
- 0782US6833737B2SOI sense amplifier method and apparatusIBM·Filed 2003·Granted Dec 21, 2004·30 cites·17 claims
- 0881US8643421B1Implementing low power, single master-slave elastic bufferIBM·Filed 2013·Granted Feb 4, 2014·6 cites·17 claims
- 0981US7009905B2Method and apparatus to reduce bias temperature instability (BTI) effectsIBM·Filed 2003·Granted Mar 7, 2006·29 cites·42 claims
- 1079US6629236B1Master-slave latch circuit for multithreaded processingIBM·Filed 1999·Granted Sep 30, 2003·74 cites·17 claims
- 1178US6205063B1Apparatus and method for efficiently correcting defects in memory circuitsIBM·Filed 1998·Granted Mar 20, 2001·38 cites·24 claims
- 1278US4849904AMacro structural arrangement and method for generating macros for VLSI semiconductor circuit devicesIBM·Filed 1987·Granted Jul 18, 1989·63 cites·26 claims
- 1376US7092281B1Method and apparatus for reducing soft error rate in SRAM arrays using elevated SRAM voltage during periods of low activityIBM·Filed 2005·Granted Aug 15, 2006·9 cites·21 claims
- 1475US7725844B2Method and circuit for implementing eFuse sense amplifier verificationIBM·Filed 2008·Granted May 25, 2010·10 cites·12 claims
- 1575US6901003B2Lower power and reduced device split local and continuous bitline for domino read SRAMsIBM·Filed 2003·Granted May 31, 2005·21 cites·20 claims
- 1673US6172531B1Low power wordline decoder circuit with minimized hold timeIBM·Filed 1999·Granted Jan 9, 2001·33 cites·19 claims
- 1772US7161390B2Dynamic latching logic structure with static interfaces for implementing improved data setup timeIBM·Filed 2004·Granted Jan 9, 2007·15 cites·13 claims
- 1872US5991224AGlobal wire management apparatus and method for a multiple-port random access memoryIBM·Filed 1998·Granted Nov 23, 1999·33 cites·37 claims
- 1971US9712170B2Level-shifting latchIBM·Filed 2014·Granted Jul 18, 2017·2 cites·18 claims
- 2071US9553584B2Level-shifting latchIBM·Filed 2014·Granted Jan 24, 2017·2 cites·7 claims
- 2171US7489572B2Method for implementing eFuse sense amplifier testing without blowing the eFuseIBM·Filed 2007·Granted Feb 10, 2009·6 cites·11 claims
- 2270US9583938B2Electrostatic discharge protection device with power managementIBM·Filed 2015·Granted Feb 28, 2017·1 cites·19 claims
- 2370US6635518B2SOI FET and method for creating FET body connections with high-quality matching characteristics and no area penalty for partially depleted SOI technologiesIBM·Filed 2001·Granted Oct 21, 2003·15 cites·8 claims
- 2470US6060909ACompound domino logic circuit including an output driver section with a latchIBM·Filed 1998·Granted May 9, 2000·24 cites·13 claims
- 2569US10580730B2Managed integrated circuit power supply distributionIBM·Filed 2017·Granted Mar 3, 2020·2 cites·12 claims
- 2669US7506282B2Apparatus and methods for predicting and/or calibrating memory yieldsIBM·Filed 2005·Granted Mar 17, 2009·4 cites·20 claims
- 2768US7532057B2Electrically programmable fuse sense circuitIBM·Filed 2007·Granted May 12, 2009·4 cites·4 claims
- 2867US7289370B2Methods and apparatus for accessing memoryIBM·Filed 2005·Granted Oct 30, 2007·6 cites·16 claims
- 2967US6737685B2Compact SRAM cell layout for implementing one-port or two-port operationIBM·Filed 2002·Granted May 18, 2004·21 cites·16 claims
- 3064US7764531B2Implementing precise resistance measurement for 2D array efuse bit cell using differential sense amplifier, balanced bitlines, and programmable reference resistorIBM·Filed 2008·Granted Jul 27, 2010·5 cites·20 claims
- 3163US7729188B2Method and circuit for implementing enhanced eFuse sense circuitIBM·Filed 2008·Granted Jun 1, 2010·5 cites·20 claims
- 3261US7689950B2Implementing Efuse sense amplifier testing without blowing the EfuseIBM·Filed 2007·Granted Mar 30, 2010·3 cites·12 claims
- 3361US7239559B2Methods and apparatus for accessing memoryIBM·Filed 2005·Granted Jul 3, 2007·4 cites·20 claims
- 3460US6275427B1Stability test for silicon on insulator SRAM memory cells utilizing disturb operations to stress memory cells under testIBM·Filed 2000·Granted Aug 14, 2001·11 cites·30 claims
- 3559US9424389B2Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeperIBM·Filed 2014·Granted Aug 23, 2016·0 cites·15 claims
- 3658US11018084B2Managed integrated circuit power supply distributionIBM·Filed 2019·Granted May 25, 2021·0 cites·20 claims
- 3758US5359557ADual-port array with storage redundancy having a cross-write operationIBM·Filed 1992·Granted Oct 25, 1994·19 cites·15 claims
- 3857US7224594B2Glitch protect valid cell and method for maintaining a desired state valueIBM·Filed 2005·Granted May 29, 2007·4 cites·20 claims
- 3957US6509236B1Laser fuseblow protection method for silicon on insulator (SOI) transistorsIBM·Filed 2000·Granted Jan 21, 2003·6 cites·9 claims
- 4057US6404686B1High performance, low cell stress, low power, SOI CMOS latch-type sensing method and apparatusIBM·Filed 2001·Granted Jun 11, 2002·9 cites·19 claims
- 4155US6570433B2Laser fuseblow protection method for silicon on insulator (SOI) transistorsIBM·Filed 2001·Granted May 27, 2003·5 cites·2 claims
- 4253US9396303B2Implementing enhanced performance dynamic evaluation circuit by combining precharge and delayed keeperIBM·Filed 2015·Granted Jul 19, 2016·0 cites·5 claims
- 4353US7400550B2Delay mechanism for unbalanced read/write paths in domino SRAM arraysIBM·Filed 2006·Granted Jul 15, 2008·2 cites·3 claims
- 4451US5835502AMethod and apparatus for handling variable data word widths and array depths in a serial shared abist schemeIBM·Filed 1996·Granted Nov 10, 1998·14 cites·30 claims
- 4550US9496712B1Electrostatic discharge protection device with power managementIBM·Filed 2016·Granted Nov 15, 2016·0 cites·1 claims
- 4650US7206236B1Array redundancy supporting multiple independent repairsIBM·Filed 2006·Granted Apr 17, 2007·2 cites·17 claims
- 4749US7733722B2Apparatus for implementing eFuse sense amplifier testing without blowing the eFuseIBM·Filed 2009·Granted Jun 8, 2010·1 cites·9 claims
- 4849US5991208AWrite multiplexer apparatus and method for multiple write port programmable memoryIBM·Filed 1998·Granted Nov 23, 1999·12 cites·20 claims
- 4948US4618943ASemiconductor static read/write memory having an additional read-only capabilityIBM·Filed 1984·Granted Oct 21, 1986·7 cites·10 claims
- 5046US6260164B1SRAM that can be clocked on either clock phaseIBM·Filed 1998·Granted Jul 10, 2001·10 cites·13 claims
Showing the top 50 of 74 patent records by PatentIndex Score.
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