Inventor · disambiguated record
Anwar Ali
Also filed as: ALI ANWAR
26 granted patents·4 pending applications·296 citations·filing 1999–2023
96Inventor score
Top patents by PatentIndex Score
30 records- 0187US6836026B1Integrated circuit design for both input output limited and core limited integrated circuitsLSI LOGIC CORP·Filed 2003·Granted Dec 28, 2004·64 cites·20 claims
- 0287US6657870B1Die power distribution systemLSI LOGIC CORP·Filed 2001·Granted Dec 2, 2003·56 cites·14 claims
- 0386US12450178B2Aggregation of multiple memory modules for a system-on-chipAVAGO TECH INT SALES PTE LID·Filed 2023·Granted Oct 21, 2025·1 cites·19 claims
- 0484US6671865B1High density input outputLSI LOGIC CORP·Filed 2001·Granted Dec 30, 2003·41 cites·20 claims
- 0582US8350375B2Flipchip bump patterns for efficient I-mesh power distribution schemesLSI LOGIC CORP·Filed 2008·Granted Jan 8, 2013·11 cites·20 claims
- 0676US7554133B1Pad current splittingLSI CORP·Filed 2008·Granted Jun 30, 2009·8 cites·15 claims
- 0773US6798069B1Integrated circuit having adaptable core and input/output regions with multi-layer pad trace conductorsLSI LOGIC CORP·Filed 2003·Granted Sep 28, 2004·22 cites·31 claims
- 0870US7863716B2Method and apparatus of power ring positioning to minimize crosstalkLSI CORP·Filed 2009·Granted Jan 4, 2011·4 cites·6 claims
- 0970US7569472B2Method and apparatus of power ring positioning to minimize crosstalkLSI CORP·Filed 2006·Granted Aug 4, 2009·4 cites·7 claims
- 1070US6591410B1Six-to-one signal/power ratio bump and trace pattern for flip chip designLSI LOGIC CORP·Filed 2000·Granted Jul 8, 2003·21 cites·15 claims
- 1164US8115321B2Separate probe and bond regions of an integrated circuitALI ANWAR·Filed 2009·Granted Feb 14, 2012·4 cites·20 claims
- 1264US7117467B2Methods for optimizing package and silicon co-design of integrated circuitLSI LOGIC CORP·Filed 2004·Granted Oct 3, 2006·12 cites·32 claims
- 1353US8151237B2Disabling unused IO resources in platform-based integrated circuitsALI ANWAR·Filed 2008·Granted Apr 3, 2012·2 cites·21 claims
- 1453US7107561B2Method of sizing via arrays and interconnects to reduce routing congestion in flip chip integrated circuitsLSI LOGIC CORP·Filed 2004·Granted Sep 12, 2006·6 cites·22 claims
- 1552US7075179B1System for implementing a configurable integrated circuitLSI LOGIC CORP·Filed 2004·Granted Jul 11, 2006·6 cites·10 claims
- 1652US6784102B2Laterally interconnecting structuresLSI LOGIC CORP·Filed 2002·Granted Aug 31, 2004·6 cites·20 claims
- 1751US6768142B2Circuit component placementLSI LOGIC CORP·Filed 2002·Granted Jul 27, 2004·5 cites·11 claims
- 1850US6815812B2Direct alignment of contactsLSI LOGIC CORP·Filed 2002·Granted Nov 9, 2004·5 cites·12 claims
- 1950US6781150B2Test structure for detecting bonding-induced cracksLSI LOGIC CORP·Filed 2002·Granted Aug 24, 2004·4 cites·10 claims
- 2048US7328417B2Cell-based method for creating slotted metal in semiconductor designsLSI LOGIC CORP·Filed 2003·Granted Feb 5, 2008·1 cites·38 claims
- 2148US2025038647A1Scalable switch capacitor voltage regulatorsAVAGO TECH INT SALES PTE LID·Filed 2023·Application pending·0 cites
- 2247US6781228B2Donut power mesh scheme for flip chip packageLSI LOGIC CORP·Filed 2003·Granted Aug 24, 2004·3 cites·19 claims
- 2346US6998638B2Test structure for detecting bonding-induced cracksLSI LOGIC CORP·Filed 2004·Granted Feb 14, 2006·2 cites·10 claims
- 2442US7430730B2Disabling unused IO resources in platform-based integrated circuitsLSI CORP·Filed 2004·Granted Sep 30, 2008·2 cites·8 claims
- 2540US7737564B2Power configuration method for structured ASICsLSI CORP·Filed 2006·Granted Jun 15, 2010·0 cites·12 claims
- 2639US2013154109A1Method of lowering capacitances of conductive apertures and an interposer capable of being reverse biased to achieve reduced capacitanceVENKATRAMAN RAMNATH·Filed 2011·Application pending·0 cites
- 2738US2014312475A1Die reuse in electrical circuitsLSI CORP·Filed 2013·Application pending·0 cites
- 2837US2009160475A1Test pin reduction using package center ball grid arrayALI ANWAR·Filed 2007·Application pending·0 cites
- 2934US6683476B2Contact ring architectureLSI LOGIC CORP·Filed 2002·Granted Jan 27, 2004·0 cites·19 claims
- 3032US6704918B1Integrated circuit routingLSI LOGIC CORP·Filed 1999·Granted Mar 9, 2004·6 cites·30 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →