Inventor · disambiguated record
Andrew J. Beaumont-Smith
Also filed as: BEAUMONT-SMITH ANDREW J
24 granted patents·3 pending applications·103 citations·filing 2001–2024
94Inventor score
Technology areasG06F
Files withAPPLE INC20BEAUMONT-SMITH ANDREW J4GUNNA RAMESH B1HEWLETT PACKARD DEVELOPMENT CO1MURRAY DANIEL C1
Top patents by PatentIndex Score
27 records- 0192US11249766B1Coprocessor synchronizing instruction suppressionAPPLE INC·Filed 2020·Granted Feb 15, 2022·4 cites·20 claims
- 0291US8352685B2Combining write buffer with dynamically adjustable flush metricsAPPLE INC·Filed 2010·Granted Jan 8, 2013·16 cites·13 claims
- 0390US11755333B2Coprocessor prefetcherAPPLE INC·Filed 2021·Granted Sep 12, 2023·2 cites·20 claims
- 0489US8285947B2Store hit load predictorBEAUMONT-SMITH ANDREW J·Filed 2009·Granted Oct 9, 2012·24 cites·20 claims
- 0587US8959320B2Preventing update training of first predictor with mismatching second predictor for branch instructions with alternating pattern hysteresisBEAUMONT-SMITH ANDREW J·Filed 2011·Granted Feb 17, 2015·12 cites·21 claims
- 0685US11210104B1Coprocessor context priorityAPPLE INC·Filed 2020·Granted Dec 28, 2021·2 cites·18 claims
- 0784US11775301B2Coprocessor register renaming using registers associated with an inactive context to store results from an active contextAPPLE INC·Filed 2021·Granted Oct 3, 2023·1 cites·20 claims
- 0884US11429555B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2019·Granted Aug 30, 2022·3 cites·22 claims
- 0984US8555040B2Indirect branch target predictor that prevents speculation if mispredict is expectedBEAUMONT-SMITH ANDREW J·Filed 2010·Granted Oct 8, 2013·9 cites·22 claims
- 1082US10831488B1Computation engine with extract instructions to minimize memory accessAPPLE INC·Filed 2018·Granted Nov 10, 2020·3 cites·26 claims
- 1181US9009451B2Instruction type issue throttling upon reaching threshold by adjusting counter increment amount for issued cycle and decrement amount for not issued cycleMURRAY DANIEL C·Filed 2011·Granted Apr 14, 2015·8 cites·21 claims
- 1281US2025094381A1Coprocessors with Bypass Optimization, Variable Grid Architecture, and Fused Vector OperationsAPPLE INC·Filed 2024·Application pending·0 cites
- 1378US8364936B2Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependenciesAPPLE INC·Filed 2012·Granted Jan 29, 2013·4 cites·22 claims
- 1474US12050918B2Coprocessor prefetcherAPPLE INC·Filed 2023·Granted Jul 30, 2024·0 cites·17 claims
- 1574US2025094174A1Coprocessor PrefetcherAPPLE INC·Filed 2024·Application pending·0 cites
- 1673US12430224B2Debug trace of cache memory requestsAPPLE INC·Filed 2023·Granted Sep 30, 2025·0 cites·20 claims
- 1773US12174785B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2022·Granted Dec 24, 2024·0 cites·20 claims
- 1873US12135681B2Coprocessors with bypass optimization, variable grid architecture, and fused vector operationsAPPLE INC·Filed 2022·Granted Nov 5, 2024·0 cites·18 claims
- 1969US2024045680A1Coprocessor Register RenamingAPPLE INC·Filed 2023·Application pending·0 cites
- 2068US11740993B2Debug trace of cache memory requestsAPPLE INC·Filed 2021·Granted Aug 29, 2023·0 cites·20 claims
- 2166US8255671B2Processor employing split scheduler in which near, low latency operation dependencies are tracked separate from other operation dependenciesBEAUMONT-SMITH ANDREW J·Filed 2008·Granted Aug 28, 2012·3 cites·17 claims
- 2264US11650825B2Coprocessor synchronizing instruction suppressionAPPLE INC·Filed 2022·Granted May 16, 2023·0 cites·19 claims
- 2364US8566528B2Combining write buffer with dynamically adjustable flush metricsAPPLE INC·Filed 2012·Granted Oct 22, 2013·1 cites·17 claims
- 2463US7127483B2Method and system of a microprocessor subtraction-division floating point dividerHEWLETT PACKARD DEVELOPMENT CO·Filed 2001·Granted Oct 24, 2006·10 cites·31 claims
- 2561US11768690B2Coprocessor context priorityAPPLE INC·Filed 2021·Granted Sep 26, 2023·0 cites·20 claims
- 2658US9354886B2Maintaining the integrity of an execution return address stackGUNNA RAMESH B·Filed 2011·Granted May 31, 2016·1 cites·20 claims
- 2747US10846091B2Coprocessor with distributed registerAPPLE INC·Filed 2019·Granted Nov 24, 2020·0 cites·20 claims
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →