Inventor · disambiguated record
Anupama Bowonder
Also filed as: BOWONDER ANUPAMA
24 granted patents·10 pending applications·98 citations·filing 2009–2025
93Inventor score
Top patents by PatentIndex Score
34 records- 0196US12021149B2Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2023·Granted Jun 25, 2024·2 cites·20 claims
- 0296US8384122B1Tunneling transistor suitable for low voltage operationUNIV CALIFORNIA·Filed 2009·Granted Feb 26, 2013·78 cites·18 claims
- 0387US11462536B2Integrated circuit structures having asymmetric source and drain structuresINTEL CORP·Filed 2018·Granted Oct 4, 2022·5 cites·17 claims
- 0486US12237420B2Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2024·Granted Feb 25, 2025·0 cites·20 claims
- 0584US2025142870A1Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2024·Application pending·0 cites
- 0683US11682731B2Fin smoothing and integrated circuit structures resulting therefromINTEL CORP·Filed 2019·Granted Jun 20, 2023·2 cites·23 claims
- 0783US2025380478A1Source or drain structures with relatively high germanium contentINTEL CORP·Filed 2025·Application pending·0 cites
- 0881US11735630B2Integrated circuit structures with source or drain dopant diffusion blocking layersINTEL CORP·Filed 2019·Granted Aug 22, 2023·2 cites·20 claims
- 0980US11251302B2Epitaxial oxide plug for strained transistorsINTEL CORP·Filed 2017·Granted Feb 15, 2022·2 cites·20 claims
- 1075US11430868B2Buried etch-stop layer to help control transistor source/drain depthINTEL CORP·Filed 2018·Granted Aug 30, 2022·2 cites·20 claims
- 1171US11152461B2Semiconductor layer between source/drain regions and gate spacersINTEL CORP·Filed 2018·Granted Oct 19, 2021·1 cites·20 claims
- 1271US9117893B1Tunneling transistor suitable for low voltage operationHU CHENMING·Filed 2013·Granted Aug 25, 2015·3 cites·19 claims
- 1371US2023343826A1Integrated circuit structures with source or drain dopant diffusion blocking layersINTEL CORP·Filed 2023·Application pending·0 cites
- 1469US11984449B2Channel structures with sub-fin dopant diffusion blocking layersINTEL CORP·Filed 2022·Granted May 14, 2024·0 cites·20 claims
- 1569US11923412B2Sub-fin leakage reduction for template strained materialsINTEL CORP·Filed 2023·Granted Mar 5, 2024·0 cites·20 claims
- 1669US11757037B2Epitaxial oxide plug for strained transistorsINTEL CORP·Filed 2022·Granted Sep 12, 2023·0 cites·20 claims
- 1769US11069795B2Transistors with channel and sub-channel regions with distinct compositions and dimensionsINTEL CORP·Filed 2017·Granted Jul 20, 2021·1 cites·20 claims
- 1868US12426299B2Fin shaping and integrated circuit structures resulting therefromINTEL CORP·Filed 2022·Granted Sep 23, 2025·0 cites·11 claims
- 1961US11901457B2Fin shaping and integrated circuit structures resulting therefromINTEL CORP·Filed 2019·Granted Feb 13, 2024·0 cites·23 claims
- 2059US11600696B2Sub-fin leakage reduction for template strained materialsINTEL CORP·Filed 2019·Granted Mar 7, 2023·0 cites·16 claims
- 2158US2025220870A1Integrated circuit structure with varied epitaxial source or drain structures and device typesINTEL CORP·Filed 2023·Application pending·0 cites
- 2255US11521968B2Channel structures with sub-fin dopant diffusion blocking layersINTEL CORP·Filed 2018·Granted Dec 6, 2022·0 cites·23 claims
- 2354US12484272B2Source or drain structures with relatively high germanium contentINTEL CORP·Filed 2018·Granted Nov 25, 2025·0 cites·17 claims
- 2454US12439640B2Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistorsINTEL CORP·Filed 2021·Granted Oct 7, 2025·0 cites·12 claims
- 2550US11495683B2Multiple strain states in epitaxial transistor channel through the incorporation of stress-relief defects within an underlying seed materialINTEL CORP·Filed 2020·Granted Nov 8, 2022·0 cites·23 claims
- 2650US2023197716A1Transistors with epitaxial source/drain liner for improved contact resistanceINTEL CORP·Filed 2021·Application pending·0 cites
- 2749US2025006733A1Integrated circuit structures with differential epitaxial source or drain dentINTEL CORP·Filed 2023·Application pending·0 cites
- 2849US2024213100A1Metal gate cut with hybrid material fillINTEL CORP·Filed 2022·Application pending·0 cites
- 2949US2024332088A1Modulation of chip performance by controlling transistor gate profileINTEL CORP·Filed 2023·Application pending·0 cites
- 3048US2024222447A1Gate cut, and source and drain contactsINTEL CORP·Filed 2022·Application pending·0 cites
- 3147US2023420574A1Mobility improvement in gate all around transistors based on substrate orientationINTEL CORP·Filed 2022·Application pending·0 cites
- 3244US11374100B2Source or drain structures with contact etch stop layerINTEL CORP·Filed 2018·Granted Jun 28, 2022·0 cites·17 claims
- 3344US10886272B2Techniques for forming dual-strain fins for co-integrated n-MOS and p-MOS devicesINTEL CORP·Filed 2016·Granted Jan 5, 2021·0 cites·20 claims
- 3442US11456357B2Self-aligned gate edge architecture with alternate channel materialINTEL CORP·Filed 2018·Granted Sep 27, 2022·0 cites·19 claims
Join the waitlist — get patent alerts
Get an alert when Anupama Bowonder files or is granted a new patent.
We store only your email — no account needed. See our privacy policy.
Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →