Inventor · disambiguated record
Anthony J. Bybell
Also filed as: BYBELL ANTHONY J · BYBELL ANTHONY JOSEPH
40 granted patents·5 pending applications·177 citations·filing 2000–2020
96Inventor score
Top patents by PatentIndex Score
45 records- 0192US9323692B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 26, 2016·15 cites·13 claims
- 0292US9317443B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted Apr 19, 2016·17 cites·12 claims
- 0392US6920519B1System and method for supporting access to multiple I/O hub nodes in a host bridgeIBM·Filed 2000·Granted Jul 19, 2005·81 cites·32 claims
- 0479US9330023B2Managing translations across multiple contexts using a TLB with entries directed to multiple privilege levels and to multiple types of address spacesIBM·Filed 2014·Granted May 3, 2016·4 cites·8 claims
- 0579US8301992B2System and apparatus for error-correcting register filesBYBELL ANTHONY J·Filed 2009·Granted Oct 30, 2012·12 cites·28 claims
- 0678US9811472B2Radix table translation of memoryBYBELL ANTHONY J·Filed 2012·Granted Nov 7, 2017·4 cites·15 claims
- 0778US9600419B2Selectable address translation mechanismsIBM·Filed 2012·Granted Mar 21, 2017·4 cites·20 claims
- 0878US8751898B2Utilizing error correcting code data associated with a region of memoryBYBELL ANTHONY J·Filed 2012·Granted Jun 10, 2014·6 cites·20 claims
- 0972US8095861B2Cache function overloadingBYBELL ANTHONY J·Filed 2007·Granted Jan 10, 2012·5 cites·20 claims
- 1071US9086988B2Identification and consolidation of page table entriesIBM·Filed 2013·Granted Jul 21, 2015·2 cites·9 claims
- 1170US9864700B1Method and apparatus for power reduction in a multi-threaded modeADVANCED MICRO DEVICES INC·Filed 2016·Granted Jan 9, 2018·1 cites·20 claims
- 1270US9251092B2Hybrid address translationIBM·Filed 2013·Granted Feb 2, 2016·2 cites·8 claims
- 1369US9256550B2Hybrid address translationBYBELL ANTHONY J·Filed 2012·Granted Feb 9, 2016·2 cites·15 claims
- 1468US8245016B2Multi-threaded processingBYBELL ANTHONY J·Filed 2007·Granted Aug 14, 2012·4 cites·18 claims
- 1565US9734084B2Separate memory address translations for instruction fetches and data accessesIBM·Filed 2014·Granted Aug 15, 2017·1 cites·8 claims
- 1665US9311249B2Managing translation of a same address across multiple contexts using a same entry in a translation lookaside bufferIBM·Filed 2014·Granted Apr 12, 2016·1 cites·7 claims
- 1764US10956340B2Hardware-based pre-page walk virtual address transformation independent of page size utilizing bit shifting based on page sizeIBM·Filed 2019·Granted Mar 23, 2021·0 cites·6 claims
- 1864US9092359B2Identification and consolidation of page table entriesBYBELL ANTHONY J·Filed 2012·Granted Jul 28, 2015·1 cites·18 claims
- 1962US8782380B2Fine-grained privilege escalationBYBELL ANTHONY J·Filed 2010·Granted Jul 15, 2014·2 cites·17 claims
- 2062US7444347B1Systems, methods and computer products for compression of hierarchical identifiersIBM·Filed 2007·Granted Oct 28, 2008·7 cites·4 claims
- 2158US8135927B2Structure for cache function overloadingBYBELL ANTHONY J·Filed 2008·Granted Mar 13, 2012·1 cites·16 claims
- 2257US10146698B2Method and apparatus for power reduction in a multi-threaded modeADVANCED MICRO DEVICES INC·Filed 2017·Granted Dec 4, 2018·0 cites·20 claims
- 2357US7526419B2Methods for reconstructing data from simulation modelsIBM·Filed 2005·Granted Apr 28, 2009·1 cites·3 claims
- 2455US10216642B2Hardware-based pre-page walk virtual address transformation where the virtual address is shifted by current page size and a minimum page sizeIBM·Filed 2013·Granted Feb 26, 2019·0 cites·15 claims
- 2555US9734083B2Separate memory address translations for instruction fetches and data accessesIBM·Filed 2014·Granted Aug 15, 2017·0 cites·13 claims
- 2655US2014281209A1Hardware-based pre-page walk virtual address transformationIBM·Filed 2013·Application pending·0 cites
- 2754US9740628B2Page table entry consolidationIBM·Filed 2013·Granted Aug 22, 2017·0 cites·6 claims
- 2853US12039337B2Processor with multiple fetch and decode pipelinesADVANCED MICRO DEVICES INC·Filed 2020·Granted Jul 16, 2024·0 cites·20 claims
- 2953US11907126B2Processor with multiple op cache pipelinesADVANCED MICRO DEVICES INC·Filed 2020·Granted Feb 20, 2024·0 cites·19 claims
- 3053US9785569B2Radix table translation of memoryIBM·Filed 2013·Granted Oct 10, 2017·0 cites·8 claims
- 3153US7689400B2Reconstruction of data from simulation modelsIBM·Filed 2009·Granted Mar 30, 2010·0 cites·17 claims
- 3252US9753860B2Page table entry consolidationBYBELL ANTHONY J·Filed 2012·Granted Sep 5, 2017·0 cites·12 claims
- 3352US7742909B2Reconstruction of data from simulation modelsIBM·Filed 2009·Granted Jun 22, 2010·0 cites·7 claims
- 3452US2014101407A1Selectable address translation mechanismsIBM·Filed 2013·Application pending·0 cites
- 3550US9348763B2Asymmetric co-existent address translation structure formatsIBM·Filed 2013·Granted May 24, 2016·0 cites·10 claims
- 3649US9280488B2Asymmetric co-existent address translation structure formatsIBM·Filed 2012·Granted Mar 8, 2016·0 cites·17 claims
- 3748US8250345B2Structure for multi-threaded processingBYBELL ANTHONY J·Filed 2008·Granted Aug 21, 2012·0 cites·18 claims
- 3845US7334060B2System and method for increasing the speed of serially inputting data into a JTAG-compliant deviceIBM·Filed 2004·Granted Feb 19, 2008·2 cites·18 claims
- 3944US7181661B2Method and system for broadcasting data to multiple tap controllersIBM·Filed 2004·Granted Feb 20, 2007·2 cites·17 claims
- 4043US10037283B2Updating least-recently-used data for greater persistence of higher generality cache entriesADVANCED MICRO DEVICES INC·Filed 2016·Granted Jul 31, 2018·0 cites·17 claims
- 4143US2009287904A1System and method to enforce allowable hardware configurationsIBM·Filed 2008·Application pending·0 cites
- 4242US7558948B2Method for providing zero overhead looping using carry chain maskingIBM·Filed 2004·Granted Jul 7, 2009·0 cites·9 claims
- 4340US8140831B2Routing instructions in a processorBYBELL ANTHONY J·Filed 2009·Granted Mar 20, 2012·0 cites·19 claims
- 4440US2012144165A1Sideband payloads in pseudo no-operation instructionsBYBELL ANTHONY J·Filed 2010·Application pending·0 cites
- 4539US2007027669A1System and method for the offline development of passive simulation clientsIBM·Filed 2005·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →