Inventor · disambiguated record
Anthony D. Drumm
Also filed as: DRUMM ANTHONY · DRUMM ANTHONY D · DRUMM ANTHONY DEGROFF
19 granted patents·2 pending applications·668 citations·filing 1987–2013
95Inventor score
Top patents by PatentIndex Score
21 records- 0189US5003487AMethod and apparatus for performing timing correction transformations on a technology-independent logic model during logic synthesisIBM·Filed 1988·Granted Mar 26, 1991·111 cites·8 claims
- 0286US6643683B1Interactive client-server environment for performing collaborative timing analysis of circuit designsIBM·Filed 2000·Granted Nov 4, 2003·65 cites·31 claims
- 0386US5508937AIncremental timing analysisIBM·Filed 1993·Granted Apr 16, 1996·134 cites·32 claims
- 0477US7451416B2Method and system for designing an electronic circuitIBM·Filed 2006·Granted Nov 11, 2008·7 cites·7 claims
- 0574US6425110B1Incremental design tuning and decision mediatorIBM·Filed 1998·Granted Jul 23, 2002·69 cites·41 claims
- 0673US6601223B1System and method for fast interconnect delay estimation through iterative refinementIBM·Filed 2000·Granted Jul 29, 2003·18 cites·20 claims
- 0773US5537330AMethod for mapping in logic synthesis by logic classificationIBM·Filed 1994·Granted Jul 16, 1996·68 cites·24 claims
- 0868US7900182B2Method and system for designing an electronic circuitIBM·Filed 2008·Granted Mar 1, 2011·3 cites·18 claims
- 0968US5029102ALogical synthesisIBM·Filed 1987·Granted Jul 2, 1991·48 cites·24 claims
- 1063US5436849AIncremental logic synthesis system for efficient revision of logic circuit designsIBM·Filed 1993·Granted Jul 25, 1995·43 cites·12 claims
- 1161US8407652B2Task-based multi-process design synthesisDRUMM ANTHONY D·Filed 2010·Granted Mar 26, 2013·1 cites·23 claims
- 1261US6826740B2Automated buffer insertion incorporating congestion relief for use in connection with physical design of integrated circuitIBM·Filed 2002·Granted Nov 30, 2004·8 cites·34 claims
- 1359US8341565B2Task-based multi-process design synthesis with reproducible transformsDRUMM ANTHONY D·Filed 2010·Granted Dec 25, 2012·1 cites·23 claims
- 1459US5825661AMethod and apparatus for automatic post-layout optimization of an integrated circuitIBM·Filed 1996·Granted Oct 20, 1998·38 cites·5 claims
- 1558US8392866B2Task-based multi-process design synthesis with notification of transform signaturesDRUMM ANTHONY D·Filed 2010·Granted Mar 5, 2013·1 cites·25 claims
- 1655US7168057B2Targeted optimization of buffer-tree logicIBM·Filed 2004·Granted Jan 23, 2007·4 cites·16 claims
- 1753US8677304B2Task-based multi-process design synthesisIBM·Filed 2013·Granted Mar 18, 2014·0 cites·25 claims
- 1853US5761079AEngineering change management system employing a smart editorIBM·Filed 1997·Granted Jun 2, 1998·28 cites·7 claims
- 1948US5799170ASimplified buffer manipulation using standard repowering functionIBM·Filed 1996·Granted Aug 25, 1998·21 cites·24 claims
- 2044US2009265534A1Fairness, Performance, and Livelock Assessment Using a Loop Manager With Comparative Parallel LoopingAVERILL DUANE A·Filed 2008·Application pending·0 cites
- 2143US2007234259A1Cell placement in circuit designIBM·Filed 2006·Application pending·0 cites
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