Inventor · disambiguated record
Antony John Harris
Also filed as: HARRIS ANTONY · HARRIS ANTONY J · HARRIS ANTONY JOHN
21 granted patents·2 pending applications·188 citations·filing 2001–2021
94Inventor score
Top patents by PatentIndex Score
23 records- 0193US11537543B2Technique for handling protocol conversionADVANCED RISC MACH LTD·Filed 2021·Granted Dec 27, 2022·4 cites·20 claims
- 0289US7143221B2Method of arbitrating between a plurality of transfers to be routed over a corresponding plurality of paths provided by an interconnect circuit of a data processing apparatusADVANCED RISC MACH LTD·Filed 2004·Granted Nov 28, 2006·51 cites·13 claims
- 0383US7069376B2Flexibility of use of a data processing apparatusADVANCED RISC MACH LTD·Filed 2004·Granted Jun 27, 2006·36 cites·19 claims
- 0478US7219178B2Bus deadlock avoidanceADVANCED RISC MACH LTD·Filed 2004·Granted May 15, 2007·29 cites·33 claims
- 0576US7925840B2Data processing apparatus and method for managing snoop operationsADVANCED RISC MACH LTD·Filed 2008·Granted Apr 12, 2011·8 cites·30 claims
- 0672US8190801B2Interconnect logic for a data processing apparatusHARRIS ANTONY JOHN·Filed 2006·Granted May 29, 2012·7 cites·15 claims
- 0772US7757027B2Control of master/slave communication within an integrated circuitADVANCED RISC MACH LTD·Filed 2008·Granted Jul 13, 2010·5 cites·26 claims
- 0872US7117277B2Flexibility of design of a bus interconnect block for a data processing apparatusADVANCED RISC MACH LTD·Filed 2004·Granted Oct 3, 2006·17 cites·15 claims
- 0970US8429457B2Use of statistical representations of traffic flow in a data processing systemHARRIS ANTONY JOHN·Filed 2009·Granted Apr 23, 2013·6 cites·19 claims
- 1065US8275967B2Storage of sequentially sensitive dataHARRIS ANTONY·Filed 2008·Granted Sep 25, 2012·5 cites·23 claims
- 1163US7290075B2Performing arbitration in a data processing apparatusADVANCED RISC MACH LTD·Filed 2006·Granted Oct 30, 2007·2 cites·13 claims
- 1262US7213095B2Bus transaction management within data processing systemsADVANCED RISC MACH LTD·Filed 2004·Granted May 1, 2007·9 cites·16 claims
- 1361US9672153B2Memory interface controlLAYCOCK CHRISTOPHER WILLIAM·Filed 2011·Granted Jun 6, 2017·2 cites·29 claims
- 1461US8375170B2Apparatus and method for handling data in a cacheADVANCED RISC MACH LTD·Filed 2010·Granted Feb 12, 2013·1 cites·21 claims
- 1558US11599467B2Cache for storing coherent and non-coherent dataADVANCED RISC MACH LTD·Filed 2021·Granted Mar 7, 2023·0 cites·22 claims
- 1652US7353297B2Handling of write transactions in a data processing apparatusADVANCED RISC MACH LTD·Filed 2004·Granted Apr 1, 2008·2 cites·14 claims
- 1752US7254658B2Write transaction interleavingADVANCED RISC MACH LTD·Filed 2004·Granted Aug 7, 2007·2 cites·14 claims
- 1851US7213092B2Write response signalling within a communication busADVANCED RISC MACH LTD·Filed 2004·Granted May 1, 2007·2 cites·14 claims
- 1945US8045573B2Bit ordering for packetised serial data transmission on an integrated circuitADVANCED RISC MACH LTD·Filed 2006·Granted Oct 25, 2011·0 cites·19 claims
- 2044US10078589B2Enforcing data protection in an interconnectADVANCED RISC MACH LTD·Filed 2015·Granted Sep 18, 2018·0 cites·16 claims
- 2141US2002069251A1Method and system for high-speed transfer of data between two computers using a common targetFiled 2001·Application pending·0 cites
- 2239US8589631B2Coherency control with writeback orderingLAYCOCK CHRISTOPHER WILLIAM·Filed 2011·Granted Nov 19, 2013·0 cites·21 claims
- 2336US2013311745A1Storage of sequentially sensitive dataHARRIS ANTONY·Filed 2012·Application pending·0 cites
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Identity basis: PatentsView inventor disambiguation (2025Q4-odp release). How scoring works →